CC1111F16RSPR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
CC1111F16RSPR
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'CC1111F16RSPR' PDF : 240 Pages View PDF
13.9.3 Channel Mode Control
The channel mode is set with each channel’s
control and status register TxCCTLn.
Note: before an I/O pin can be used by the
timer, the required I/O pin must be
configured as a Timer 3/4 peripheral pin as
described in section 13.4.6 on page 64.
13.9.4 Output Compare Mode
In output compare mode the I/O pin
associated with a channel is set as an output.
After the timer has been started, the contents
of the counter are compared with the contents
of the channel compare register TxCCn. If the
compare register equals the counter contents,
the output pin is set, reset, or toggled
according to the compare output mode setting
of TxCCTLn.CMP. Note that all edges on
output pins are glitch-free when operating in a
given compare output mode. Writing to the
compare register TxCC0 does not take effect
on the output compare value until the counter
value is 0x00. Writing to the compare register
TxCC1 takes effect immediately.
When a compare occurs, the interrupt flag for
the appropriate channel (TIMIF.TxCHnIF) is
asserted. The IRCON.TxIF flag is only
asserted if the corresponding interrupt mask
bit TxCCTLn.IM is set to 1. An interrupt
request is generated if the corresponding
interrupt mask bit is set together with
IEN1.TxEN. When operating in up-down
mode, the interrupt flag for channel 0 is set
when the counter reaches 0x00 instead of
when a compare occurs.
For simple PWM use, output compare modes
3 and 4 are preferred.
13.9.5 Timer 3 and 4 Interrupts
There is one interrupt vector assigned to each
of the timers. These are T3 and T4 (interrupt
#11 and #12, see Table 39). The following
timer events may generate an interrupt
request:
• Counter reaches terminal count value
(overflow) or turns around on zero /
reach zero
• Output compare event
The register bits TIMIF.T3OVFIF,
TIMIF.T4OVFIF,
TIMIF.T3CH0IF,
TIMIF.T3CH1IF, TIMIF.T4CH0IF, and
TIMIF.T4CH1IF contains the interrupt flags
for the two terminal count value event
CC1110Fx / CC1111Fx
(overflow), and the four channel compare
events, respectively. These flags will be
asserted regardless off the channel n interrupt
mask bit (TxCCTLn.IM). The CPU interrupt
flag, IRCON.TxIF will only be asserted if one
or more of the channel n interrupt mask bits
are set to 1. An interrupt request is only
generated when the corresponding interrupt
mask bit is set together with IEN1.TxEN. The
interrupt mask bits are T3CCTL0.IM,
T3CCTL1.IM, T4CCTL0.IM, T4CCTL1.IM,
T3CTL.OVFIM, and T4CTL.OVFIM. Note that
enabling an interrupt mask bit will generate a
new interrupt request if the corresponding
interrupt flag is set.
When the timer is used in Free-running Mode
or Modulo Mode the interrupt flags are set as
follows:
• TIMIF.TxCH0IF
and
TIMIF.TxCH1IF are set on compare
event
• TIMIF.TxOVFIF is set when counter
reaches terminal count value (overflow)
When the timer is used in Down Mode the
interrupt flags are set as follows:
• TIMIF.TxCH0IF
and
TIMIF.TxCH1IF are set on compare
event
• TIMIF.TxOVFIF is set when counter
reaches zero
When the timer is used in Up/Down Mode the
interrupt flags are set as follows:
• TIMIF.TxCH0IF
and
TIMIF.TxOVFIF are set when the
counter turns around on zero
• TIMIF.TxCH1IF is set on compare
event
In addition, the CPU interrupt flag,
IRCON.TxIF will be asserted if the channel n
interrupt mask bit (TxCCTLn.IM) is set to 1.
13.9.6 Timer 3 and Timer 4 DMA Triggers
There are two DMA triggers associated with
Timer 3 and two DMA triggers associated with
Timer 4. These are DMA triggers T3_CH0,
T3_CH1, T4_CH0, and T4_CH1, which are
generated on timer compare events as follows:
• T3_CH0: Timer 3 channel 0 compare
• T3_CH1: Timer 3 channel 1 compare
• T4_CH0: Timer 4 channel 0 compare
• T4_CH1: Timer 4 channel 1 compare
SWRS033E
Page 133 of 239
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