CC1111F16RSPR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
CC1111F16RSPR
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'CC1111F16RSPR' PDF : 240 Pages View PDF
CC1110Fx / CC1111Fx
Register
Name
U0GCR
U1CSR
U1DBUF
U1BAUD
U1UCR
U1GCR
ENDIAN
WDCTL
SFR
Module
Address
Description
0xC5
USART0
USART 0 Generic Control
0xF8
USART1
USART 1 Control and Status
0xF9
USART1
USART 1 Receive/Transmit Data Buffer
0xFA
USART1
USART 1 Baud Rate Control
0xFB
USART1
USART 1 UART Control
0xFC
USART1
USART 1 Generic Control
0x95
MEMORY
USB Endianess Control (CC1111Fx)
0xC9
WDT
Watchdog Timer Control
Table 31: CC1110Fx/CC1111Fx Specific SFR Overview
Retention5
Y
Y
Y
Y
Y,[7]N
Y
Y
Y
11.2.3.4 Radio Registers
The radio registers are all related to Radio
configuration and control. The RF registers can
only be accessed through XDATA memory
space and reside in address range 0xDF00 -
0xDF3D.
Table 32 gives a descriptive overview of these
registers. Each register is described in detail in
section 14.19, starting on page 208.
XDATA Register
Address
0xDF00 SYNC1
0xDF01 SYNC0
0xDF02 PKTLEN
0xDF03 PKTCTRL1
0xDF04 PKTCTRL0
0xDF05 ADDR
0xDF06 CHANNR
0xDF07 FSCTRL1
0xDF08 FSCTRL0
0xDF09 FREQ2
0xDF0A FREQ1
0xDF0B FREQ0
0xDF0C MDMCFG4
0xDF0D MDMCFG3
0xDF0E MDMCFG2
0xDF0F MDMCFG1
0xDF10 MDMCFG0
0xDF11 DEVIATN
0xDF12 MCSM2
0xDF13 MCSM1
0xDF14 MCSM0
0xDF15 FOCCFG
0xDF16 BSCFG
Description
Sync word, high byte
Sync word, low byte
Packet length
Packet automation control
Packet automation control
Device address
Channel number
Frequency synthesizer control
Frequency synthesizer control
Frequency control word, high byte
Frequency control word, middle byte
Frequency control word, low byte
Modem configuration
Modem configuration
Modem configuration
Modem configuration
Modem configuration
Modem deviation setting
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Frequency Offset Compensation configuration
Bit Synchronization configuration
Retention6
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
6 Registers without retention are in their reset state after PM2 or PM3. This is only applicable for
registers / bits that are defined as R/W
SWRS033E
Page 50 of 239
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