CC2430F64RTC View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
CC2430F64RTC
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'CC2430F64RTC' PDF : 212 Pages View PDF
Peripherals : MAC Timer (Timer2)
CC2430
T2OF0 (0xA1) – Timer 2 Overflow Count 0
Bit Name
7:0 OF0[7:0]
Reset R/W
0x00
R/W
Description
Overflow count. Low bits T2OF[7:0]. T2OF is incremented by 1 each
time the timer overflows i.e. timer counts to a value greater or equal to
period. Writing to this register when the timer is in IDLE or RUN states
will force the overflow count to be set to the value written to
T2OF2:T2OF1:T2OF0. If the count would otherwise be incremented by
1 when this register is written then 1 is added to the value written. The
value written will not take effect until T2OF2 is written.
T2CAPHPH (0xA5) – Timer 2 Period High Byte
Bit Name
7:0 CAPHPH[7:0]
Reset R/W
0xFF
R/W
Description
Capture value high/timer period high. Writing this register sets the high
order bits [15:8] of the timer period. Reading this register gives the high
order bits [15:8] of the timer value at the last capture event.
T2CAPLPL (0xA4) – Timer 2 Period Low Byte
Bit Name
7:0 CAPLPL[7:0]
Reset R/W
0xFF
R/W
Description
Capture value low/timer period low. Writing this register sets the low
order bits [7:0] of the timer period. Reading this register gives the low
order bits [7:0] of the timer value at the last capture event.
T2PEROF2 (0x9E) – Timer 2 Overflow Capture/Compare 2
Bit Name
7
CMPIM
Reset R/W
0
R/W
6
PERIM
0
R/W
5
OFCMPIM
0
R/W
4
-
3:0 PEROF2[3:0]
0
R0
0000
R/W
Description
Compare interrupt mask.
0: No interrupt is generated on compare event
1: Interrupt is generated on compare event.
Overflow interrupt mask
0: No interrupt is generated on timer overflow
1: Interrupt is generated on timer overflow
Overflow count compare interrupt mask
0: No interrupt is generated on overflow count compare
1: Interrupt is generated on overflow count compare
Not used, read as 0
Overflow count capture/Overflow count compare value. Writing these
bits set the high bits [19:16] of the overflow count compare value.
Reading these bits returns the high bits [19:16] of the overflow count
value at the time of the last capture event.
T2PEROF1 (0x9D) – Timer 2 Overflow Capture/Compare 1
Bit Name
7:0 PEROF1[7:0]
Reset R/W
0x00
R/W
Description
Overflow count capture /Overflow count compare value. Writing these
bits set the middle bits [15:8] of the overflow count compare value.
Reading these bits returns the middle bits [15:8] of the overflow count
value at the time of the last capture event.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 115 of 211
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