CC2430F64RTCR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
Part Name
Description
MFG CO.
CC2430F64RTCR
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS
'CC2430F64RTCR' PDF : 212 Pages View PDF
CC2430
Peripherals : USART
At the end of the transfer, the received data
byte is available for reading from UxDBUF
The transmit interrupt is generated at the start
of the operation.
13.14.3 SSN Slave Select Pin
When the USART is operating in SPI mode,
configured as an SPI slave, a 4-wire interface
is used with the Slave Select (SSN) pin as an
input to the SPI (edge controlled). At falling
edge of SSN the SPI slave is active and
receives data on the MOSI input and outputs
data on the MISO output. At rising edge of
SSN, the SPI slave is inactive and will not
receive data. Note that the MISO output is not
tri-stated after rising edge on SSn. Also note
that release of SSn (rising edge) must be
aligned to end of byte recived or sent. If
released in a byte the next received byte will
not be received properly as information about
previous byte is present in SPI system. A
USART flush can be used to remove this
information.
In SPI master mode, the SSN pin is not used.
When the USART operates as an SPI master
and a slave select signal is needed by an
external SPI slave device, then a general
purpose I/O pin should be used to implement
the slave select signal function in software.
13.14.4 Baud Rate Generation
An internal baud rate generator sets the UART
baud rate when operating in UART mode and
the SPI master clock frequency when
operating in SPI mode.
The
UxBAUD.BAUD_M[7:0]
and
UxGCR.BAUD_E[4:0] registers define the
baud rate used for UART transfers and the
rate of the serial clock for SPI transfers. The
baud rate is given by the following equation:
Baudrate = (256 + BAUD _ M ) ∗ 2 BAUD _ E ∗ F
2 28
where F is the system clock frequency, 16
MHz (calibrated RC osc.) or 32 MHz (crystal
osc.).
The register values required for standard baud
rates are shown in Table 43 for a typical
system clock set to 32 MHz. The table also
gives the difference in actual baud rate to
standard baud rate value as a percentage
error.
The maximum baud rate for UART mode is
F/16 when BAUD_E is 16 and BAUD_M is 0,
and where F is the system clock frequency.
The maximum baud rate for SPI master mode
and thus SCK frequency is F/8. This is set
when BAUD_E is 17 and BAUD_M is 0. If SPI
master mode does not need to receive data
the maximum SPI rate is F/2 where BAUD_E
is 19 and BAUD_M is 0. Setting higher baud
rates than this will give erroneous results. For
SPI slave mode the maximum baud rate is
always F/8.
Note that the baud rate must be set through
the UxBAUD and registers UxGCR before any
other UART or SPI operations take place. This
means that the timer using this information is
not updated until it has completed its start
conditions, thus changing the baud rate take
time.
Table 43: Commonly used baud rate settings for 32 MHz system clock
Baud rate (bps)
2400
4800
9600
14400
19200
28800
38400
57600
76800
115200
230400
UxBAUD.BAUD_M
59
59
59
216
59
216
59
216
59
216
216
UxGCR.BAUD_E
6
7
8
8
9
9
10
10
11
11
12
Error (%)
0.14
0.14
0.14
0.03
0.14
0.03
0.14
0.03
0.14
0.03
0.03
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 145 of 211
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