CC2430F64RTCR View Datasheet(PDF) - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS

Part Name

Description

MFG CO.

CC2430F64RTCR

A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee®

TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS 

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CC2430

Peripherals : DMA Controller

13.5.5 DMA Interrupts

Each DMA channel can be configured to

generate an interrupt to the CPU upon

completing a DMA transfer. This is

accomplished with the IRQMASK bit in the

channel configuration. The corresponding

interrupt flag in the DMAIRQ SFR register will

be set when the interrupt is generated.

Regardless of the IRQMASK bit in the channel

configuration, the interrupt flag will be set upon

DMA channel complete. Thus software should

always check (and clear) this register when

rearming a channel with a changed IRQMASK

setting. Failure to do so could generate an

interrupt based on the stored interrupt flag.

13.5.6 DMA Configuration Data Structure

For each DMA channel, the DMA configuration

data structure consists of eight bytes. The

13.5.7 DMA memory access

The DMA data transfer is affected by endian

convention. This as the memory system use

Big-Endian in XDATA memory, while Little-

configuration data structure is described in

Table 42.

Endian is used in SFR memory. This must be

accounted for in compilers.

CC2430 Data Sheet (rev. 2.1) SWRS036F

Page 93 of 211

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