CDB42406 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CDB42406

Evaluation Board For CS42406

Cirrus Logic 

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CDB42406

1.7.2d Setup 6

An external DSP connected to DSP I/O HDR, masters all clocks for the ADC/DAC. For

implementation of this setup option, set DIP switch S4 (SW[3:0]) to ‘0110’b.

AU D IO

MCLK

CS8416

RMCK

O MCK

OLR C K/

OS CL K

S DO UT

CS8406

OMCK

ILR CK /

IS CL K

S D IN

CS42406

M CLK

D AC _LR CK /

DAC_SCL K

D AC _S DIN x

ADC_ LRCK/

ADC_ SCLK

A DC _S DO UT

DSP I/O

HDR

DSP_ MCL K

D SP _D AC _LR CK /

DSP_DAC_SCL K

D SP _S DIN x

D SP _A DC _LR CK /

DSP_ADC_SCL K

DSP_SDO UT

Figure 7. Digital Loopback - Setup 6

1.7.3 DSP Routing

There are 6 different setup options for routing MCLK, LRCK and SCLK for DSP control.

These options allow either shared or independent control over the subclocks for the DAC

and ADC. The user may also choose between 2 different MCLK sources.

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