CDB4383 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDB4383' PDF : 40 Pages View PDF
CS4383
5.6 Using DSD mode
In stand-alone mode, DSD operation is selected by
holding DSD_EN(LRCK) high and applying the
DSD data and clocks to the appropriate pins. The
M2:0 pins set the expected DSD rate and MCLK
ratio.
In control-port mode the FM bits set the device into
DSD mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected
DSD rate and MCLK ratio.
During DSD operation, the PCM related pins
should either be tied low or remain active with
clocks (except LRCK in Stand-Alone mode).
When the DSD related pins are not being used they
should either be tied static low, or remain active
with clocks (except M3 in Stand-Alone mode).
6. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The CS4383 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written from register 01h to 08h and then from
09h and 11h, allowing block reads or writes of suc-
cessive registers in two separate sections (the
counter will not auto-increment to register 09h
from register 08h).
6.1 Enabling the Control Port
On the CS4383 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
is done by performing a I2C or SPI write. Once the
control port is enabled, these pins are dedicated to
control port functionality.
To prevent audible artifacts the CPEN bit (see Sec-
tion 3.1.1) should be set prior to the completion of
the Stand-Alone power-up sequence, approximate-
ly 1024 LRCK cycles. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; how-
ever, setting this bit after the Stand-Alone power-
up sequence has completed can cause audible arti-
facts.
6.2 Format Selection
The control port has 2 formats: SPI and I2C, with
the CS4383 operating as a slave device.
If I2C operation is desired, AD0/CS should be tied
to VLC or GND. If the CS4383 ever detects a high
to low transition on AD0/CS after power-up and af-
ter the control port is activated , SPI format will be
selected.
6.3 I2C Format
In I2C Format, SDA is a bidirectional data line.
Data is clocked into and out of the part by the clock,
SCL, with a clock to data relationship as shown in
Figure 7. The receiving device should send an ac-
knowledge (ACK) after each byte received. There
is no CS pin. Pin AD0 forms the partial chip ad-
dress and should be tied to VLC or GND as re-
quired. The upper 6 bits of the 7 bit address field
must be 001100.
Note: MCLK is required during all I2C transac-
tions. Please see reference 4 for further details.
6.3.1 Writing in I2C Format
To communicate with the CS4383, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol-
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