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CDH2D09 View Datasheet(PDF) - Maxim Integrated

Part Name
Description
MFG CO.
'CDH2D09' PDF : 44 Pages View PDF
PMIC with Integrated Charger and
Smart Power Selector for Handheld Devices
Pin Description (continued)
PIN
NAME
FUNCTION
23
LX1
Inductor Switching Node for REG1. LX1 is internally pulled to PG1 by 1kΩ in shutdown.
24
PG1
Power Ground for the REG1 Step-Down Regulator
25
PG3
Power Ground for the REG3 Step-Down Regulator
26
LX3
Inductor Switching Node for REG3. LX3 is internally pulled to PG3 by 1kΩ in shutdown.
27
PV3
Power Input for the REG3 Step-Down Regulator. Connect PV3 to SYS. Bypass PV3 to PG3 with a
4.7µF ceramic capacitor.
IC Supply Output. VL is an LDO output that powers the MAX8671X internal battery-charger circuitry.
28
VL
VL provides 3.3V at 3mA to power external circuitry when DC or USB is present. Connect a 0.1µF
capacitor from VL to AGND.
29
FB3
Feedback Input for REG3. Connect FB3 to the center of a resistor voltage-divider from the REG3
output capacitors to AGND to set the output voltage from 1V to VSYS.
30
DISET
DC Input Current-Limit Select Input. Connect a resistor from DISET to AGND (RDISET) to set the DC
current limit. See Table 2 for more information.
31
CISET
Charge Rate Select Input. Connect a resistor from CISET to AGND (RCISET) to set the fast-charge
current limit, prequalification-charge current limit, and top-off threshold.
Charge Timer Programming Node. Connect a capacitor from CT to AGND (CCT) to set the time
32
CT
required for a fault to occur in fast-charge or prequalification modes. Connect CT to AGND to disable
the fast-charge and prequalification timers.
Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor that has a good
33
THM
thermal contact with the battery from THM to AGND. Connect a resistor equal to the thermistor
resistance at +25°C from THM to VL. Charging is suspended when the battery is outside the hot or
cold limits.
34
BAT
Positive Battery Terminal Connection. Connect BAT to the positive terminal of a single-cell Li+/Li-Poly
battery.
System Supply Output. Bypass SYS to power ground with a 10µF ceramic capacitor.
When a valid voltage is present at USB or DC and not suspended (USUS = low), SYS is limited to
35
SYS
5.3V (VSYS-REG). When the system load (ISYS) exceeds the input current limit, SYS drops below VBAT
by VBSREG allowing both the external power source and the battery service SYS.
SYS is connected to BAT through an internal system load switch (RBS) when a valid source is not
present at USB or DC.
36
PEN1 Input Current-Limit Control 1. See Table 1 for more information.
37
CST2
Open-Drain Charger Status Output 2. CST1 and CST2 indicate four different charger states. See
Table 3 for more information.
38
UOK
Active-Low, Open-Drain USB Power-OK Output. UOK is low when VUSB is within its valid operating
range.
39
CST1
Open-Drain Charger Status Output 1. CST1 and CST2 indicate four different charger states. See
Table 3 for more information.
40
PEN2 Input Current-Limit Control 2. See Table 1 for more information.
EP
Exposed Paddle. Connect the exposed paddle to AGND. Connecting the exposed paddle does not
remove the requirement for proper ground connections to AGND, PG1, PG2, and PG3.
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