CDK2000-CLK View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDK2000-CLK' PDF : 26 Pages View PDF
6.3.3
CS2100-OTP
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl
0
1
Application:
Clock Output Enable Status
Clock outputs are driven ‘low’ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 16
6.3.4
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio .
LFRatioCfg
0
1
Application:
Ratio Bit Encoding Interpretation
20.12 - High Multiplier.
12.20 - High Accuracy.
“User Defined Ratio (RUD)” on page 14
6.3.5
M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin.
M2Config[2:0]
000
001
010
011
100
101
110
111
Application:
M2 pin function
Disable CLK_OUT pin.
Disable AUX_OUT pin.
Disable CLK_OUT and AUX_OUT.
RModSel[1:0] Modal Parameter Enable.
Reserved.
Reserved.
Reserved.
Force AuxOutSrc[1:0] = 10 (PLL Clock Out).
“M2 Mode Pin Functionality” on page 18
6.3.6
Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0]
000
001
010
011
100
101
110
111
Application:
Minimum Loop Bandwidth
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
128 Hz
“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 13
22
DS841F1
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