CDK8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDK8920A' PDF : 144 Pages View PDF
4.0 PACKETPAGE ARCHITECTURE
4.1 PacketPage Overview
The CS8920A architecture is based on a unique,
highly-efficient method of accessing internal reg-
isters and buffer memory known as PacketPage.
PacketPage provides a unified way of controlling
the CS8920A in Memory or I/O space that mini-
mizes CPU overhead and simplifies software. It
provides a flexible set of performance features
and configuration options, allowing designers to
develop Ethernet circuits that meet their particu-
lar system requirements.
Integrated Memory
Central to the CS8920A architecture is a 4-Kbyte
page of integrated RAM known as PacketPage
memory. PacketPage memory is used for tempo-
rary storage of transmit and receive frames, and
for internal registers. Access to this memory is
done directly, through Memory space operations
(Section 4.11), or indirectly, though I/O space
operations (Section 4.12). In most cases, Mem-
ory Mode will provide the best overall
performance, because ISA Memory operations
require fewer cycles than I/O operations. I/O
Mode is the CS8920A’s default configuration and
is used when memory space is not available or
when special operations are required (e.g. wak-
ing the CS8920A from the Software Sleep state
requires the host to write to the CS8920A’s as-
signed I/O space).
The user-accessible portion of PacketPage mem-
ory is organized into the following sections:
PacketPage
Address
Contents
0000h - 0048h Product/Bus Specific Registers
0100h - 013Fh Status and Normal Control Registers
0120h
Interrupt Status Queue
0140h - 015Dh Ethernet, or Line, Related Registers
0330h - 03FFh Plug and Play Registers
0400h - 09FFh Current Receive Frame Virtual Map
0A00h - 0FFFh Current Transmit Frame Virtual Map
DS238PP2
CS8920A
Bus Interface Registers
The Bus Interface registers are used to configure
the CS8920A’s ISA-bus interface and to map the
CS8920A into the host system’s I/O and Mem-
ory space. Most of these registers are written
only during initialization, remaining unchanged
while the CS8920A is in normal operating mode.
The exceptions to this are the DMA registers
which are modified continually whenever the
CS8920A is using DMA. These registers are de-
scribed in more detail in Section 4.3.
Status and Control Registers
The Status and Control registers are the primary
means of controlling and getting status of the
CS8920A. They are described in more detail in
Section 4.4.
Initiate Transmit Registers
The TxCMD/TxLength registers are used to initi-
ate Ethernet frame transmission. These registers
are described in more detail in Section 4.6. (See
Section 5.8 for a description of frame transmis-
sion.)
Address Filter Registers
The Filter registers store the Individual Address
filter and Logical Address filter used by the Des-
tination Address (DA) filter. These registers are
described in more detail in Section 4.7. For a de-
scription of the DA filter, see Section 5.3.
Plug and Play Registers
Plug and Play registers hold resources assigned
by a plug and play configuration manager. These
resources include IO and memory base address,
interrupt number and DMA channel. See section
4.8.
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