CDK8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDK8920A' PDF : 144 Pages View PDF
CS8920A
Register 9: Transmit Command Status (TxCMD, Read-only)
Address: PacketPage base + 0108h
F
E
D
C
B
A
9
8
7
6
5-0
TxPadDis InhibitCRC
Onecoll Force
TxStart
001001
This register contains the latest transmit command which tells the CS8920A how the next packet should be sent.
The command must be written to PacketPage base + 0144h in order to initiate a transmission. The host can read
the command from register 9 (PacketPage base + 0108h). See Section 5.8.
BIT NAME
5-0 001001
7, 6 TxStart
8
Force
9
Onecoll
C InhibitCRC
D TxPadDis
DESCRIPTION
These bits provide an internal address used by the CS8920A to identify this as the
Transmit Command Register. When reading this register, these bits will be 001001,
where the LSB corresponds to Bit 0.
This pair of bits determines how many bytes are transferred to the CS8920A before the
MAC starts the packet transmit process.
Bit 7 Bit 6
0 0 Start transmission after 5 bytes are in the CS8920A
0 1 Start transmission after 381 bytes are in the CS8920A
1 0 Start transmission after 1021 bytes are in the CS8920A
1 1 Start transmission after the entire frame is in the CS8920A
When set in conjunction with a new transmit command, any transmit frames waiting in
the transmit buffer are deleted. If a previous packet has started transmission, that
packet is terminated within 64 bit times with a bad CRC.
When this bit is set, any transmission will be terminated after only one collision. When
clear, the CS8920A allows up to 16 normal collisions before terminating the
transmission.
When set, the CRC is not appended to the transmission.
When TxPadDis is clear, and the host gives a transmit length less than 60 bytes and
InhibitCRC is set, the CS8920A pads to 60 bytes. If the host gives a transmit length
less than 60 bytes and InhibitCRC is clear, the CS8920A pads to 60 bytes and
appends the CRC.
When TxPadDis is set, the CS8920A allows transmission of runt frames (a frame less
than 64 bytes). If InhibitCRC is clear, the CS8920A appends the CRC. If InhibitCRC is
set, the CS8920A does not append the CRC.
After reset, if no EEPROM is found by the CS8920A, the register has the following initial state. If an EEPROM is
found, the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000 0000 1001
NOTE:
The CS8920A does not transmit a frame if TxLength < 3.
56
DS238PP2
Share Link: 
