CDK8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDK8920A' PDF : 144 Pages View PDF
CS8920A
Register 1D: Auto Negotiation Control (AutoNegCTL, Read/Write)
F
E
D
C
B
A
9
ForceFDX
NLP
Enable
Address: PacketPage base + 011Ch
8
7
6
5-0
AutoNeg AllowFDX ReNOW 011101
Enable
BIT NAME
5-0 011101
6
ReNOW
DESCRIPTION
These bits provide an internal address used by the CS8920A to identify this as the Test
Control Register.
When set, and when NLPEnable and ForceFDX are not set, a re-negotiation is forced.
ReNOW clears itself after re-negotiation begins. Reset value is 0.
7
AllowFDX
When set, the FDX mode is advertised. AllowFDX is sampled only when entering the
Ability Detect state during arbitration. Changes to this bit are ignored after arbitration
begins. To re-sample this bit, a re-negotiation must be forced.
8
AutoNegEnable When set, and when NLPEnable and ForceFDX are not set, auto negotiation may
occur, including using fast link pulses. When AutoNegEnable is clear, negotiations are
aborted, including the negotiation in progress. Reset value is 0. When AutoNegEnable
bit is cleared, set bit ReNOW.
9
NLPEnable When set, the normal link pulses will be transmitted and auto negotiation will be
disabled. Reset value is 0.
F
ForceFDX
This bit is used to force full duplex operation. The FDXLED output is asserted to show
(10BASE-T, that full duplex operation is being used. FDXactive is also set and auto negotiation
only)
capability will be disabled. When ForceFDX is clear, the full duplex operation is not
forced, but the CS8920A may be in full duplex due to auto negotiation.
NOTE:
One of the bits, either F, 9, or 8, must be set to allow a link to be established. If none of the bits are set,
no link pulses of any kind will be sent, and the transmitter will be disabled.
This register’s initial state after reset is: 0000 0000 0001 1101
70
DS238PP2
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