CDK8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CDK8920A' PDF : 144 Pages View PDF
entire frame from host memory to CS8920A
memory.
For a more detailed description of transmit, see
Section 5.8.
Basic I/O Mode Receive
I/O Mode receive operations occur in the follow-
ing order (In this example, interrupts are enabled
to signal the presence of a valid receive frame):
1.A frame is received by the CS8920A, trigger-
ing an enabled interrupt.
2.The host reads the Interrupt Status Queue Port
(I/O base + 0008h) and is informed of the re-
ceive frame.
3.The host reads the frame data by executing re-
petitive read instructions (REP IN) from the
Receive/Transmit Data Port (I/O base + 0000h)
to transfer the frame from CS8920A memory
to host memory. Preceding the frame data are
the contents of the RxStatus register (Packet-
Page base + 0400h) and the RxLength register
(PacketPage base + 0402h).
For a more detailed description of receive, see
Section 5.2.
Accessing Internal Registers
To access any of the CS8920A’s internal registers
in I/O Mode, the host must first set up the Pack-
etPage Pointer. It does this by writing the
PacketPage address of the target register to the
PacketPage Pointer Port (I/O base + 000Ah).
The content of the target register is then mapped
into the PacketPage Data Port (I/O base +
000Ch).
When the host needs to access a sequential block
of registers, the MSB of the PacketPage address
of the first word to be accessed should be set to
1. The PacketPage Pointer will then move to the
next word location automatically, eliminating the
CS8920A
need to set up the PacketPage Pointer between
successive accesses (see Figure 4.4).
Polling the CS8920A in I/O Mode
If interrupts are not used, the host can poll the
CS8920A to check if receive frames are present
and if memory space is available for transmit.
DS238PP2
85
Share Link: 
