CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
10.1.3 Gen Map 0–6 End Address Low (I/O)
Register Name: Gen Map 0–6 End Address Low (I/O)
I/O Index: 0Ah, 0Eh, 12h, 1Ah, 22h, 2Ah, 32h
Memory Offset: 80Ah, 80Eh, 812h, 81Ah, 822h, 82Ah, 832h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Per: socket
Register Compatibility Type: 365
Bit 2
Bit 1
Bit 0
End Address 7:0 (I/O)
R/W:00000000
There are seven separate Gen Map End Address Low registers, each with identical fields. These
registers are located at the following indexes:
Index
0Ah
0Eh
12h
1Ah
22h
2Ah
32h
Memory Offset
80Ah
80Eh
812h
81Ah
822h
82Ah
832h
Gen Map End Address Low
Gen Map 5 End Address Low
Gen Map 6 End Address Low
Gen Map 0 End Address Low
Gen Map 1 End Address Low
Gen Map 2 End Address Low
Gen Map 3 End Address Low
Gen Map 4 End Address Low
Default Operation
I/O Window 0
I/O Window 1
Memory Window 0
Memory Window 1
Memory Window 2
Memory Window 3
Memory Window 4
Bits 7:0 — End Address 7:0 (I/O)
This register contains the least-significant byte of the address that specifies where the I/O space
corresponding to the I/O map ends. I/O accesses that are equal or below this address and equal
or above the corresponding Gen Map Start Address are mapped into the I/O or memory space of
the corresponding PC Card.
June 1998
ADVANCE DATA BOOK v0.3
GENERAL WINDOW MAPPING
REGISTERS
121
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