CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
3.1.7
Socket Power Management Features
3.1.7.1 Socket Power Control
The CL-PD6833 provides two pins to serially control the socket power. These pins have multiple function-
ality to allow the CL-PD6833 to interface with a number of socket power-control chips. Following are the
two socket power-control signalling modes supported by the CL-PD6833:
q Texas Instruments TPS2206AIDF Serial Signalling mode
q SMBus™ (system management bus)1 Signalling mode using the Maxim 1601
The socket power-control signalling mode is usually established during power-on reset by the level of pins
131 (SDATA/SMBDATA) and 130 (SLATCH/SMBCLK), but it can also be set by writing to bit 2 of the Misc
Control 3 register. Refer to Table 3-5 for the configuration of the power-control signalling mode.
Table 3-5. Socket Power Control Configuration
Socket Power Signalling Mode
Texas Instruments TPS2206AIDF or
External Hardware Serial Mode
SMBus (system management bus)
SLATCH/SMBCLK
(Pin 130)
Pull-down
Pull-up
Misc Control 3
Bit 2
0
1
Texas Instruments TPS2206AIDF Serial Signalling Mode
In this mode, the CL-PD6833 can interface with the Texas Instruments TPS2206AIDF dual-socket PC
Card power interface switch, which uses a three-pin interface: SCLK, SDATA, and SLATCH (refer to
Figure 3-10). The pin SCLK is connected to the 10–100-kHz (usually 32-kHz) clock typically available on
the system. This serves as a reference clock for the CL-PD6833 and as a clock to the TPS2206AIDF. The
data is serially transferred over SDATA and the latch signal is SLATCH.
SDATA/SMBDATA (131)
SLATCH/SMBCLK (130)
CL-PD6833
SCLK (132)
SDATA
SLATCH
RST#
SDATA
SLATCH
SHDN#
TPS2206AIDF
SCLK
SCLK
Figure 3-10. Power Control Using Texas Instruments
TPS2206AIDF Serial Signalling Mode
1 SMBus is a trademark of Intel® Corporation.
June 1998
ADVANCE DATA BOOK v0.3
35
INTRODUCTION TO THE CL-PD6833
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