CL-PS7110-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VC-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
are driven onto the least heavily loaded address lines in a typical system, thus reducing overall system
power.
CL-PS7110 uses a system of logic interlocks and timeouts to ensure that the device both enters Standby
mode safely and restarts properly as the main oscillator starts. If external signals indicate that the main
battery power level is low, the system will not attempt to wake up, thus avoiding a possible loss of volatile
memory contents due to the failure of both main and backup batteries.
While the CPU is processing instructions, CL-PS7110 is in its normal operating state. By writing to a reg-
ister location, the idle state can be entered, with both oscillators still running. In this state, DMA for video
can continue but the processor clock is stopped pending an interrupt.
1.2.21 Software Model for Power Management
The following section shows how to enter various modes:
Idle mode
setup timer1
enable timer1 interrupt
halt the CPU (write to HWHalt register at 0x8000 0800)
On an interrupt (interrupts must be enabled), the system automatically wakes up and returns to operating
mode.
Standby mode
setup RTC Match value
enable RTC match interrupt
Write to STDBY register at 0x8000 0840
On an interrupt (interrupts must be enabled), the system automatically returns to normal operating mode.
1.2.22 Resets
There are three asynchronous resets to the CL-PS7110: NPOR, NPWRFL, and NURESET. If any of these
are active, a system reset is generated internally. This clears all internal registers in the CL-PS7110 to ‘0’,
except the DRAM Refresh Period register (DRFPR) and the Realtime Clock Data register (RTCDR),
which are only cleared by an active NPOR signal. This also resets the ARM710A and causes it to start
execution at the reset vector when the CL-PS7110 returns to its normal operating mode.
Internal to the CL-PS7110, three different signals are used to reset storage elements: NPOR, NSYSRES,
and RUN. NPOR and RUN are also external signals.
NPOR (Not Power On Reset)
This is the highest-priority reset signal. When active-low, it resets all storage elements in the CL-PS7110.
NPOR active forces NSYSRES active and run low. NPOR is usually only active after the CL-PS7110 is
first powered up. NPOR active clears all flags in the status register, apart from the Cold Flag (CLDFLG)
bit, which is set.
May 1997
DATA BOOK v1.5
29
FUNCTIONAL DESCRIPTION
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