CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
I/O registers are the exception. Reading or writing an I/O register may have side effects, so a single 16-
bit access is needed. A byte access may trigger a side effect before the other byte is transferred, and a
word access could affect neighboring I/O registers. To provide 16-bit-wide accesses, no bus width con-
version is done for word accesses. Instead, there is a single bus cycle with only data bits D0 to D15 valid.
If alignment fault checking is enabled in the ARM710A core, all word accesses require a word-aligned
address, that is both A0 and A1 must be zero. To access the 16-bit I/O registers that are not at word-
aligned addresses (that is, A1 is one), the CL-PS7110 makes special use of address bit 25. For a PCMCIA
bank, if address bits A25 to A27 are all ones, the A25 output pin is driven low and the A1 output pin is
driven high.This restricts 16-bit accesses to the low 32 Mbytes of the PCMCIA I/O space, but allows
access to all registers in this range.
1.2.6 DRAM Controller
The DRAM controller in the CL-PS7110 provides all connections to directly interface up to four banks of
DRAM. Each bank is 32-bits wide and up to 256 Mbytes in size. Four RAS lines are provided, one per
bank and four CAS lines are provided, one per byte line. As the DRAM device size is not programmable,
if devices are used that are smaller than the largest size supported (1 Gbit) this leads to a segmented
memory map, each bank being separated by 256 Mbytes. Segments that are smaller than the bank size
repeat within the bank. Table 1-2 shows the mapping of physical address to DRAM row and column
address. This mapping has been organized to support any DRAM device size from 4 Mbit to 1 Gbit with
a ‘square’ row and column configuration, that is, the number of column addresses is equal to the number
of row addresses. If a non-square DRAM is used, further fragmentation of the memory map can occur;
however, the smallest contiguous segment is always 1 Mbyte.
In addition to supporting standard refresh cycles, self-refresh DRAM is supported such that system
DRAM can be put into a low-power state by the ARM710A before entering its low-power Standby mode.
DMA takes priority over other external memory or I/O accesses under the control of the internal bus arbi-
ter. Requests for more data are received from the FIFO buffer at the front end of the datapath through the
LCD controller. The DMA request is serviced by providing a quad word of data from the frame buffer that
starts at location zero in main DRAM memory. Meanwhile the CPU continues execution, including
accesses to the other peripherals. Refer to Section 1.2.10 on page 21 for the description of the LCD con-
troller.
1.2.7 PCMCIA Support
As mentioned in Section 1.2.5 (expansion memory controller), there are eight separate linear memory
segments supported and one can use one of the segments to interface with a PCMCIA card.
To design a PCMCIA-card interface to support 3/5-V cards and hot insertion, isolation buffers for address
and data will be required. A sample design is provided in CL-PS7110 Evaluation kit. A PAL (22LV10) is
used to decode PCMCIA card signals out of the CL-PS7110 address and control bus. The PAL equations
are available in the Evaluation Kit User’s Manual.
Table 1-2. Physical-to-DRAM Address Mapping
Memory
Address
0
1
DRAM
Column
A2
A3
DRAM Row Pin Name
A10
A27/DRA0
A11
A26/DRA1
May 1997
DATA BOOK v1.5
19
FUNCTIONAL DESCRIPTION
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