CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4
GRAYSCALE
GRAYSCALE
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
4 BITS PER PIXEL
PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4
GRAYSCALE GRAYSCALE GRAYSCALE GRAYSCALE
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
2 BITS PER PIXEL
PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
1 BIT PER PIXEL
Figure 1-5. Video Buffer Mapping
The refresh rate is not affected by the number of bits per pixel. However, the LCD controller fetches twice
the data per refresh for 4-bits-per-pixel compared to 2-bits-per-pixel. The main reason for reducing the
number of bits per pixel is to reduce the power consumption of the DRAMs in bank 0 where the video
buffer is mapped.
1.2.11 Internal UART and SIR Encoder
The CL-PS7110 contains a built-in UART, which offers similar functionality to the National Semiconduc-
tor® 16C550 device. It can support bit rates of up to 115.2 kbps and contains two 16-byte FIFOs for
receive and transmit.
Only three modem-control input signals are supported: CTS, DSR, and DCD. The additional RI input
modem control line is not supported. Output modem control lines (such as, RTS and DTR) are not explic-
itly supported, but can be implemented using bits from the general-purpose PIA ports in the CL-PS7110.
22
FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5
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