CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
GND VDD
-VEE
L3
47 µH
D12
C2 + C78
2.2 µ 10 µF
GND GND
R56
R
1N5818 TR1
PNP
R54
330 k
VREF
11
+
10 -
VDD
U13D
13
LM339
R65
C44
100 n
R64
R63
R62
VDD GND
R53
100 k
R74
100 k
U19
DRIVE1
FB1
82 DRIVE0
81 DRIVE1
87 FB0
86 FB1
R75
100 k
806 k
392 k
200 k
100 k
VDD
64 PD4
63 PD5
62 PD6
61 PD7
CL-PS7110
Figure 1-7. Sample Schematic for Negative VEE Control Circuitry
1.2.15 Keyboard Control
A keyboard can be connected using any of the serial channels. The CL-PS7110 provides a seamless
interface for connecting a scanning keyboard. There are column (COL[0-7]) pins for connecting to the 8
columns of the scanning keyboard. The GPIO pins can be used for row addressing; the GPIO pins 0–8
can be configured as a single 8-bit port (PA[0–7]).
1.2.16 GPIO
There are 36 general-purpose pins on CL-PS7110. These pins are user-configurable as input or output.
The 36 pins can be arranged as 4-byte-wide registers (which can also be read back as a single 32-bit
word), and one nibble-wide port (described as Port A, Port B, Port C, Port D and Port E in the device pin
diagram). Four of the I/O pins have extra-high drive output buffers to allow direct drive of an LED, for exam-
ple.
1.2.17 Buzzer Control
There a single pin for buzzer control. When the BZMOD bit of the SYSCON register (described in
Section 3.2.11) is reset, the bit BZTOG can be used to drive the buzzer directly. Otherwise, Timer 1 can
be programmed to activate the buzzer based on a pre-programmed value.
26
FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5
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