CL-PS7110-VI-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VI-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
NSYSRES (Not System Reset)
NSYSRES is generated internally to the CL-PS7110 if NPOR, NPWRFL, or NURESET are active.
NSYSRES is the second-highest-priority reset signal, used to asynchronously reset most internal regis-
ters in the CL-PS7110. NSYSRES active forces RUN low. NSYSRES resets the CL-PS7110 and forces
it into the standby state with no cooperation from software; the ARM710A is also reset. The memory con-
troller places all DRAMs in Self-Refresh mode, preserving the contents through a system reset. This is
why the DRAM Refresh Period register is not cleared by a system reset.
RUN
The RUN signal is high when the CL-PS7110 is in the operating or idle states, and low when in the standby
state. The main system clock (MMCLK) is valid when RUN is high. RUN disables any peripheral block that
is clocked from the main oscillator.
In general, a system reset clears all registers and RUN disables all peripherals that require a main clock.
The following peripherals are disabled by a low level on RUN: UART (internal UART and IrDA SIR
encoder), LCD (LCD controller), DCPMP (DC-to-DC converter drive), codec (codec interface) and SSI
(synchronous serial interface).
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FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5
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