CL-PS7500FE-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7500FE-QC-A' PDF : 251 Pages View PDF
CL-PS7500FE
System-on-a-Chip for Internet Appliance
7.5.3 Registers
The ARM processor contains registers that control the cache and MMU operation. These registers are
accessed using CPRT instructions to coprocessor #15 with the processor in a privileged mode.
Only some of registers 0–7 are valid:
q An access to an invalid register causes neither the access or an undefined instruction trap, and therefore
should never be carried out.
q An access to any of the registers 8–15 cause the undefined instruction trap to be taken.
Table 7-3. Cache and MMU Control Registers
Register
0
1
2
3
4
5
6
7
8–15
Register Reads
CPU ID
Reserved
Reserved
Reserved
Reserved
Fault Status
Fault Address
Reserved
Reserved
Register Writes
Reserved
Control
Translation Table Base
Domain Access Control
Reserved
Flush TLB
Purge TLB
Flush IDC
Reserved
June 1997
ADVANCE DATA BOOK v2.0
63
REGISTER DESCRIPTIONS
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