CL10K100E View Datasheet(PDF) - Clear Logic
Part Name
Description
MFG CO.
'CL10K100E' PDF : 18 Pages View PDF
LIBERATOR
CL10K50S
Key Features
u Fully Compatible to the Altera® FLEX® 10KS Family
u Prototype Your System With Altera FPGAs
PRELIMINARY u Seamlessly Migrate Production To Clear Logic
u No ASIC Engineering, No NRE, And No Test Vector
Development
u Very Fast, Dense Signal Routing Using Vertical Link
Interconnect
u "Gate Array" Option Eliminates Configuration EPROMs
u Fabricated Using 0.25 Micron CMOS Process
u Very Low Power Consumption (Active And Standby)
u High Density
- 50,000 Usable Gates
- 2,880 Logic Elements
- 40,960 RAM Bits
- 254 Maximum User I/O Pins
CL10KE Product Family Overview
Parameter
Typical Gates
(Logic and RAM)
Maximum System Gates
Logic Elements
Embedded Array Blocks
Total RAM Bits
Max User I/O pins
Speed Grades
Packages
CL10K30E
30,000
119,000
1,728
6
24,576
220
-1, -2, -3
144-pin TQFP
208-pin PQFP
256-pin FBGA
484-pin FBGA
CL10K50E
CL10K50S
50,000
199,000
2,880
10
40,960
254
-1, -2, -3
144-pin TQFP
208-pin PQFP
240-pin PQFP
256-pin FBGA
356-pin SBGA
484-pin FBGA
June 2001
CL10K100E
100,000
257,000
4,992
12
49,152
338
-1, -2, -3
208-pin PQFP
240-pin PQFP
256-pin FBGA
356-pin SBGA
484-pin FBGA
CL10K200E
CL10K200S
200,000
513,000
9,984
24
98,304
470
-1, -2, -3
240-pin PQFP
356-pin SBGA
484-pin FBGA
600-pin SBGA
672-pin FBGA
10KE tbl 01
Page 1
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