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CL10K50SBC356-2X View Datasheet(PDF) - Clear Logic

Part Name
Description
MFG CO.
CL10K50SBC356-2X
Clear-Logic
Clear Logic 
'CL10K50SBC356-2X' PDF : 18 Pages View PDF
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LIBERATOR CL10K50S (PRELIMINARY)
AC Electrical Specifications cont.
Interconnect Timing Parameters[5]
Speed: -1
Symbol
Parameter
Min Max
tDIN2IOE
Delay from dedicated input pin to IOE control
input
4.1
tDIN2LE
Delay from dedicated input pin to LE or EAB
control input
0.9
tDIN2DATA
Delay from dedicated input or clock pin to LE
or EAB data
1.8
tDCLK2IOE Delay from dedicated clock pin to IOE clock
3.9
tDCLK2LE
Delay from dedicated clock pin to LE or EAB
clock
0.9
tSAMELAB Delay from an LE to LE in same LAB
0.1
Speed: -2
Min Max
4.6
1.0
1.9
4.6
1.0
0.1
Speed: -3
Min Max Unit
5.9
ns
1.3
ns
2.3
ns
6.2
ns
1.3
ns
0.2
ns
tSAMEROW
Delay for driving a row IOE, LE or EAB to a
row IOE, LE or EAB in the same row
1.3
1.3
1.8
ns
tSAMECOLUMN Delay from an LE to IOE in the same column
0.7
0.8
1.5
ns
tDIFFROW
Delay for driving a column IOE, LE or EAB to
an LE or EAB in a different row
2.0
2.1
3.3
ns
tTWOROWS
Delay for driving a row IOE or EAB to an LE or
EAB in a different row
3.3
3.4
5.1
ns
tLEPERIPH
Delay from an LE to IOE control signal via the
peripheral contol bus
3.8
4.1
5.3
ns
tLABCARRY
Delay from an LE carry-out signal to an LE
carry-in signal in a different LAB
0.1
0.1
0.2
ns
tLABCASC
Delay from an LE cascade-out signal to an
LE cascade-in signal in a different LAB
0.3
0.3
0.5
ns
10KE tbl 09C
Page 13
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