CL1K100 View Datasheet(PDF) - Clear Logic
Part Name
Description
MFG CO.
'CL1K100' PDF : 16 Pages View PDF
LIBERATOR
CL1K100
Key Features
u Fully Compatible to the Altera® ACEX® 1K Family
u Prototype Your System With Altera FPGAs
PRELIMINARY u Seamlessly Migrate Production To Clear Logic
u No ASIC Engineering, No NRE, And No Test Vector
Development
u Very Fast, Dense Signal Routing Using Vertical Link
Interconnect
u "Gate Array" Option Eliminates Configuration EPROMs
u Fabricated Using 0.35 Micron CMOS Process
u Very Low Power Consumption (Active And Standby)
u High Density
- 100,000 Usable Gates
- 4,992 Logic Elements
- 49,152 RAM Bits
- 333 Maximum User I/O Pins
CL1K Product Family Overview
Parameter
Typical Gates
(Logic and RAM)
Maximum System Gates
Logic Elements
Embedded Array Blocks
Total RAM Bits
Max User I/O pins
Speed Grades
CL1K30
30,000
119,000
1,728
6
24,576
171
-1, -2, -3
Packages
144-pin TQFP
208-pin PQFP
256-pin FBGA
CL1K50
50,000
199,000
2,880
10
40,960
249
-1, -2, -3
144-pin TQFP
208-pin PQFP
256-pin FBGA
484-pin FBGA
January 2001
CL1K100
100,000
257,000
4,992
12
49,152
333
-1, -2, -3
208-pin PQFP
256-pin FBGA
484-pin FBGA
1K tbl 01
Page 1
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