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CL1K30FC256-1 View Datasheet(PDF) - Clear Logic

Part Name
Description
MFG CO.
CL1K30FC256-1
Clear-Logic
Clear Logic 
'CL1K30FC256-1' PDF : 16 Pages View PDF
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LIBERATOR CL1K30 (PRELIMINARY)
AC Electrical Specifications cont.
EAB Timing Parameters[5]
Symbol
Parameter
tEABAA EAB Address Access Delay
tEABRCCOMB EAB Asynchronous Read Cycle Time
tEABRCREG EAB Synchronous Read Cycle Time
tEABWP EAB Write Pulse Width
tEABWCCOMB EAB Asynchronous Write Cycle Time
tEABWCREG EAB Synchronous Write Cycle Time
tEABDD EAB Data-in to Data-out Delay
tEABDATACO
EAB Clock-to-output Delay Using Output
Regis ters
Speed: -1
Min Max
6.4
6.4
4.4
2.5
6.0
6.8
5.7
0.8
tEABDATASU
EAB Data/Address Setup Time Using Input
Regis ter
1.5
tEABDATAH
EAB Data/Address Hold Time Using Input
Regis ter
0.0
tEABWESU EAB WE Setup When Using Input Register
1.3
tEABWESH
EAB WE Hold Time When Using Input
Regis ter
0.0
tEABWDSU
EAB Data Setup Time to Falling Edge of
Write Pulse When Not Using Input Registers
1.5
Speed: -2
Min Max
7.6
7.6
5.1
2.9
7.0
7.8
6.7
0.9
1.7
0.0
1.4
0.0
1.7
Speed: -3
Min Max
10.2
Unit
ns
10.2
ns
7.0
ns
3.9
ns
9.5
ns
10.6
ns
9.0
ns
1.3
ns
2.3
ns
0.0
ns
2.0
ns
0.0
ns
2.3
ns
tEABWDH
EAB Data Hold Time After Falling Edge of
Write Pulse When Not Using Input Registers
0.0
0.0
0.0
ns
tEABWASU
EAB Address Setup Time to Rising Edge of
Write Pulse When Not Using Input Registers
3.0
3.6
4.8
ns
EAB Address Hold Time After Falling Edge
tEABWAH of Write Pulse When Not Using Input
0.5
0.5
0.8
ns
Regis ters
tEABWO EAB WE to Data Output Delay
5.1
6.0
8.1
ns
1K tbl 11
Page 13
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