Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

CLC1003 View Datasheet(PDF) - Cadeka Microcircuits LLC.

Part Name
Description
MFG CO.
CLC1003
CADEKA
Cadeka Microcircuits LLC. CADEKA
'CLC1003' PDF : 16 Pages View PDF
Prev 11 12 13 14 15 16
Data Sheet
The first place to start is to determine the source resis-
tance. If it is very small an additional resistance may need
to be added to keep the values of Rf and Rg to practical
levels. For this analysis we assume that Rt is the total re-
sistance present on the non-inverting input. This gives us
one equation that we must solve:
Where Vorext is the noise due to the external resistors and
is given by:
2
vo
=
en
1 + RF
RG
2
+
eG
RF
RG
2
+
e
2
F
Rt = Rg||Rf
This equation can be rearranged to solve for Rg:
Rg = (Rt * Rf) / (Rf - Rt)
The other consideration is desired gain (G) which is:
The complete equation can be simplified to:
( ) ( ) ( ) 2
vo
=
3
4kT G RT
+
2
2
enG + 2 inRT
G = (1 + Rf/Rg)
By plugging in the value for Rg we get
Rf = G * Rt
And Rg can be written in terms of Rt and G as follows:
Rg = (G * Rt) / (G - 1)
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
( ) ( ) 2
2
VI OS = VIO + IOS RT
And the output offset is:
( ) ( ) 2
2
VO OS = G V IO + I OS RT
It’s easy to see that the effect of amplifier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
large Rt values at lower gains.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
Rg
+–
Rf
+–
Rg
+–
+–
CLC1003
+
+
RL
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Figure 7: Complete Equivalent Noise Circuit
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
The complete noise equation is given by:
( ) 2
vo
=
2
vorext
+
en
1 + RF
RG
2
+
ibp RT
1 + RF
RG
2
2
+ ibnRF
Evaluation Board #
Products
CEB002
CLC1003 in SOT23-5
CEB003
CLC1003 in SOIC-8
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com 14
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]