CLC1003IST5MTR View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'CLC1003IST5MTR' PDF : 17 Pages View PDF
CLC1003
Rt = Rg||Rf
This equation can be rearranged to solve for Rg:
Rg = (Rt * Rf) / (Rf - Rt)
The other consideration is desired gain (G) which is:
G = (1 + Rf/Rg)
By plugging in the value for Rg we get
Rf = G * Rt
And Rg can be written in terms of Rt and G as follows:
Rg = (G * Rt) / (G - 1)
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
( ) ( ) 2
2
VI OS = VIO + IOS ∗ RT
And the output offset is:
( ) ( ) 2
2
VO OS = G ∗ V IO + I OS ∗ RT
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
Rg
+–
Rf
+–
+–
+
–
Rg
+–
–
CLC1003
+
RL
The complete equation can be simplified to:
( ) ( ) ( ) 2
vo
=
3∗
4kT ∗ G ∗ RT
+
2
enG + 2 ∗
2
in∗ RT
It’s easy to see that the effect of amplifier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
large Rt values at lower gains.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
■■ Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
■■ Place the 6.8µF capacitor within 0.75 inches of the power pin
■■ Place the 0.1µF capacitor within 0.1 inches of the power pin
■■ Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
■■ Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
CEB003
Products
CLC1003 in TSOT
CLC1003 in SOIC
Figure 7: Complete Equivalent Noise Circuit
The complete noise equation is given by:
( ) 2
vo
=
2
vorext
+
en
1 + RF
RG
2
+
ibp ∗ RT
1 + RF
RG
2
2
+ ibn∗ RF
Where Vorext is the noise due to the external resistors and
is given by:
2
vo
=
en
1 + RF
RG
2
+
eG ∗
RF
RG
2
+
e
2
F
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 8-12 These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
© 2007-2014 Exar Corporation
14 / 17
exar.com/CLC1003
Rev 1D
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