CLC1006IST5X View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'CLC1006IST5X' PDF : 16 Pages View PDF
Data Sheet
2.5
2
SOIC-8
1.5
1
0.5
SOT23-5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 3. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
RS, between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 4.
Input
+
-
Rf
Rg
Rs
Output
CL
RL
reducing RS will increase bandwidth at the expense of ad-
ditional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLC1006 will typically recover in less
than 25ns from an overdrive condition. Figure 5 shows the
CLC1006 in an overdriven condition.
3
5
VIN = 2.5Vpp
G=5
4
2
3
2
1 Input
1
0
Output
0
-1
-1
-2
-3
-2
-4
-3
0
-5
20 40 60 80 100 120 140 160 180 200
Time (ns)
Figure 5. Overdrive Recovery
Figure 4. Addition of RS for Driving
Capacitive Loads
Table 1 provides the recommended RS for various capaci-
tive loads. The recommended RS values result in <=1dB
peaking in the frequency response. The Frequency Re-
sponse vs. CL plots, on page 7, illustrates the response of
the CLC1006.
CL (pF)
RS (Ω)
-3dB BW (MHz)
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards
to use as a guide for high frequency layout and as aid in
device testing and characterization. Follow the steps be-
low as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
20
20
300
50
15
210
100
11
150
500
6
68
1000
3.3
55
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
©2007-2013 Exar Corporation
13/16
Rev 1D
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