CLRC632 View Datasheet(PDF) - NXP Semiconductors.
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Description
MFG CO.
'CLRC632' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
9.4.1 Interrupt sources overview
Table 20 shows the integrated interrupt flags, related source and setting condition. The
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows:
• the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern
• the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady = logic 1
• when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready = logic 1
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 20) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to
logic 1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 20) and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to
logic 1.
Table 20. Interrupt sources
Interrupt flag
Interrupt source
TimerIRq
timer unit
TxIRq
transmitter
CRC coprocessor
EEPROM
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
receiver
Command register
FIFO buffer
FIFO buffer
Trigger action
timer counts from 1 to 0
a data stream, transmitted to the card, ends
all data from the FIFO buffer has been processed
all data from the FIFO buffer has been
programmed
a data stream, received from the card, ends
command execution finishes
FIFO buffer is full
FIFO buffer is empty
9.4.2 Interrupt request handling
9.4.2.1 Controlling interrupts and getting their status
The CLRC632 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
Table 21. Interrupt control registers
Register
Bit 7
Bit 6
InterruptEn
SetIEn
reserved
InterruptRq
SetIRq
reserved
Bit 5
TimerIEn
TimerIRq
Bit 4
TxIEn
TxIRq
Bit 3
RxIEn
RxIRq
Bit 2
IdleIEn
IdleIRq
Bit 1
HiAlertIEn
HiAlertIRq
Bit 0
LoAlertIEn
LoAlertIRq
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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