GMSK Modem
CMX589A
The signal at Tx Out is centered around VBIAS, going positive for logic ‘1’ (high) level inputs to the Tx Data input
and negative for logic ‘0’ (low) inputs.
When the transmit circuits are put into a powersave mode (by a logic ‘1’ to the Tx PS pin) the output voltage of
the Tx Filter will go to high impedance. When power is subsequently restored to the Tx filter, its output will take
several bit-times to settle. The Tx Enable input can be used to prevent these abnormal voltages from
appearing at the Tx Out pin.
Figure 8: Rx and Tx Clock Data Timings
© 1998 Consumer Microcircuits Limited
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