CMX641AP4 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX641AP4' PDF : 26 Pages View PDF
Dual SPM/Security Detector/Generator
CMX641A
Controlled Sensitivity Mode (PRESET LEVEL pin = logic ‘0’)
This mode allows the sensitivity to be set from a µController via a 6-bit serial data input. This same
serial input also sets operation (bit 0) for either 12kHz or 16kHz systems. Both channels are set
identically.
Serial
Data Bits
D5-D1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
12kHz System
16kHz System
Bit D0 = ‘1’
Bit D0 = ‘0’
Bandpass Minimum
Nominal
Maximum Minimum
Nominal Maximum
Filter Gain Sensitivity Sensitivity Sensitivity Sensitivity Sensitivity Sensitivity
(dB)
dB(ref.)
dB(ref.)
dB(ref.)
dB(ref.)
dB(ref.)
dB(ref.)
0
-16.2
-17.5
-18.8
-16.9
-18.2
-19.5
1.0
-17.2
-18.5
-19.8
-17.9
-19.2
-20.5
2.0
-18.2
-19.5
-20.8
-18.9
-20.2
-21.5
3.0
-19.2
-20.5
-21.8
-19.9
-21.2
-22.5
4.0
-20.2
-21.5
-22.8
-20.9
-22.2
-23.5
5.0
-21.2
-22.5
-23.8
-21.9
-23.2
-24.5
6.0
-22.2
-23.5
-24.8
-22.9
-24.2
-25.5
7.0
-23.2
-24.5
-25.8
-23.9
-25.2
-26.5
8.0
-24.2
-25.5
-26.8
-24.9
-26.2
-27.5
9.0
-25.2
-26.5
-27.8
-25.9
-27.2
-28.5
10.0
-26.2
-27.5
-28.8
-26.9
-28.2
-29.5
11.0
-27.2
-28.5
-29.8
-27.9
-29.2
-30.5
12.0
-28.2
-29.5
-30.8
-28.9
-30.2
-31.5
13.0
-29.2
-30.5
-31.8
-29.9
-31.2
-32.5
14.0
-30.2
-31.5
-32.8
-30.9
-32.2
-33.5
15.0
-31.2
-32.5
-33.8
-31.9
-33.2
-34.5
16.0
-32.2
-33.5
-34.8
-32.9
-34.2
-35.5
17.0
-33.2
-34.5
-35.8
-33.9
-35.2
-36.5
18.0
-34.2
-35.5
-36.8
-34.9
-36.2
-37.5
19.0
-35.2
-36.5
-37.8
-35.9
-37.2
-38.5
20.0
-36.2
-37.5
-38.8
-36.9
-38.2
-39.5
21.0
-37.2
-38.5
-39.8
-37.9
-39.2
-40.5
22.0
-38.2
-39.5
-40.8
-38.9
-40.2
-41.5
23.0
-39.2
-40.5
-41.8
-39.9
-41.2
-42.5
24.0
-40.2
-41.5
-42.8
-40.9*
-42.2*
-43.5*
25.0
-41.2
-42.5
-43.8
-41.9*
-43.2*
-44.5*
26.0
-42.2
-43.5
-44.8
-42.9*
-44.2*
-45.5*
27.0
-43.2
-44.5
-45.8
-43.9*
-45.2*
-46.5*
These states should never be used. If sensitivities of this order are required, (e.g. the Swedish Rural
SPM specification, it is recommended that the Controlled sensitivity setting is set to 20dB (10100)
and external components selected to set the Input Amp gain to a higher figure.
Table 2 Controlled Sensitivity Setting Information in Fixed Bandwidth Operating State
The figures in Table 2 assume:
1. The recommended amplifier components (see figure 2) are employed.
2. The applied VDD is 5.0V. 0dB(ref.) = 775Vrms.
3. Signal sensitivity is proportional to VDD. However, the 16kHz settings marked * (11000 to 11011)
are allowed for 5V operation only.
4. Bandwidth setting 00 (±1.5%), 01 (±3/0%) or 10 (±5.0%) is selected. Add 0.5dB to upper figure if
bandwidth setting 11 (±7.5%) is selected.
Table 2 shows the serial data input to produce the required sensitivity. Minimum, nominal and maximum
sensitivity figures are provided to make complete allowance for internal circuit offsets and component
tolerances. The gain of each bandpass filter, and hence the device sensitivity, is adjusted by the applied
serial bits D1 to D5. The system frequency is selected by bit D0 (‘1’ = 12kHz; ‘0’ = 16kHz). Data is loaded
bit 5 (D5) first (See Figure 7).
© 2002 Consumer Microcircuits Limited
12
D/641A/5
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