CMX641AP4 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX641AP4' PDF : 26 Pages View PDF
Dual SPM/Security Detector/Generator
CMX641A
1.7.1.3 Operating Characteristics (continued)
Notes:
1. At 5.0V. Not including any current drawn from the pins by external circuitry.
2. At 3.0V. Not including any current drawn from the pins by external circuitry.
3. Logic pins with no internal pullup or pulldown resistors; CHIP SELECTN, SERIAL DATA,
SERIAL CLOCK, OP ENABLEN, OP SELECT and CLOCK IN pins.
4. Logic pins with an internal pullup or pulldown resistor; PRESET LEVEL/TONE ASK,
SYSTEM SELECT/TX TONE SELECT, ENHANCED FEATURES.
5. Tone Follower or Packet Mode enabled.
6. Tristate selected.
7. Time taken to change between any two of the operational modes: Tone follower, Packet or
Tristrate, and with a maximum capacitive load of 30pF on an output.
8. With adherence to Signal to Voice and Signal to Noise specifications.
9. 12kHz system.
10. 16kHz system
11. The time delay after a valid serial data load (or after device powerup, change of bandwidth
setting or change in input signal conditions), before the condition of the outputs can be
guaranteed correct.
12. With ‘Will Detect’ bandwidth set to ±1.5%, Fixed Bandwidth Operating State or Enhanced
Features Operating State.
13. With ‘Will Detect’ bandwidth set to ±3.0%, Enhanced Features Operating State only.
14. With ‘Will Detect’ bandwidth set to ±5.0%, Enhanced Features Operating State only.
15. With ‘Will Detect’ bandwidth set to ±7.5%, Enhanced Features Operating State only.
16. With the input amplifier gain at 0dB and the Bandpass filter gain set to 0dB (Table 2);
subtract 1dB from this specification for each single dB of Bandpass filter gain programmed.
Alternatively, with the input components as recommended in Figure 2, the sensitivity is as
defined in Table 2.
17. In Fixed Bandwidth Operating State, Controlled Sensitivity mode; or in Enhanced Features
Operating State.
18. In Fixed Bandwidth Operating State, Preset Sensitivity mode.
19. With input amplifier gain setting 0dB via external components and measured at amplifier
output.
20. Signal sensitivity is proportional to VDD.
21. For immunity to false responses and/or deresponses.
22. Common mode SPM and balanced voice signal.
23. With SPM and voice signal balanced; to avoid false deresponses due to saturation, the peak
to peak voice + noise level at the output of the input amplifier should be no greater than the
dynamic range of the device. For this reason, the signal to voice figure at the Amp output
will vary with the sensitivity setting. The lowest signal to voice figure occurs at the highest
sensitivity setting (Table 2, 27dB).
24. Maximum voice frequencies = 3.4kHz.
25. Output tone = 12kHz selected.
26. Output tone = 16kHz selected.
27. The time between a logic ‘1-0’ transition at TONE ASK input and the tone at TONE OP
reaching 10% of its full value or between a ‘0-1’ transition at TONE ASK input and the tone
falling to 90% of its full value.
28. The time for the tone at TONE OP to rise from 10% to 90% or to fall from 90% to 10% of its
full value.
29. Tx circuit enabled in Enhanced Features Operating State.
© 2002 Consumer Microcircuits Limited
22
D/641A/5
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