Dual SPM/Security Detector/Generator
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CMX641A Advance Information
6.1.4 Timing
Parameter
tPWH Serial Clock ‘High’ Pulse Width
tPWL Serial Clock ‘Low’ Pulse Width
tCYC Serial Clock Period
tCSE Chip Select ‘Low’ to Clock ‘High’ Edge
tDH Data Hold Time
tDS Data Setup Time
tCSH Chip Select ‘High’ from:
Clock ‘High’ Edge
Clock ‘High’ Edge
Min.
250
250
600
450
50.0
250
Typ.
-
-
-
-
-
-
Max.
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
50.0
-
-
-
-
ns
1
Serial clock period
Table 10: Data Load Timing
CHIP SELECTN
SERIAL CLOCK
SERIAL DATA
tCSE
tCYC
tCSH
tDS
tDH
tPWL
tPWH
BIT D15
Don't
Care
Data
BIT D14
D13
BIT D0
Figure 7: Data Load Timing for the Fixed Bandwidth Operating Style, Controlled Sensitivity Mode
CHIP SELECTN
SERIAL CLOCK
SERIAL DATA
tCSE
tCYC
tCSH
tDS
tDH
tPWL
tPWH
BIT D5
Don't
Care
Data
BIT D4
D3
BIT D0
Figure 8: Data Load Timing for Enhanced Features Operating State
ã2001 MX-COM, Inc.
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Doc. # 20480227.002
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