CMX644AD2 View Datasheet(PDF) - MX-COM Inc
Part Name
Description
MFG CO.
'CMX644AD2' PDF : 31 Pages View PDF
Bell 212A / V.22 Modem with Call Progress and DTMF
23
CMX644A Preliminary Information
If the time constant of R24 and C22 is large enough then the voltage on RT will remain below the threshold of
the 'B' Schmitt trigger for the duration of a ring cycle.
The time for the voltage on RT to charge from VSS towards VDD can be derived from the formula
t
=
−RC
ln1-
VRT
VDD
As the Schmitt trigger high-going input threshold voltage (VtHI) has a minimum value of 0.56 x VDD, then the
Schmitt trigger B output will remain high for a time of at least 0.821 x R24 x C22 following a pulse at RD.
The values of R24 and C22 given in Figure 12 (470kΩ and 0.33µF) give a minimum RT charge time of
100ms, which is adequate for ring frequencies of 10Hz or above.
Note that the circuit will also respond to a telephone line voltage reversal. If necessary the µC can distinguish
between a Ring signal and a line voltage reversal by measuring the time that bit 6 of the TONES DETECT
register (RING DETECT) is high.
5.3 Software Protocol for Transmitting PSK Data Bytes
In order to transmit PSK data, the following steps should be followed. For clarity, not all bit settings are
described here (but HI/LO Band, Equalization, Guard Tones, Number of Stop Bits, etc. should be set as
appropriate).
1. Program SETUP register for correct crystal frequency. Wait at least 20ms if device was previously in
‘Zero Power’ mode before proceeding.
2. Set Tx Gain Block (GAIN BLOCKS Register $E2) to required gain. Set UART mode.
3. Load first data byte into TX DATA BYTE Register ($E3).
4. Read FLAGS Register ($EF) in order to clear it.
5. Set IRQ MASK BITS Register ($EE Bits 2 and 1) to allow appropriate interrupts (TX DATA UNDERFLOW
and TX DATA READY). Note: If an underflow occurs, continuous mark (‘1’) will be transmitted.
6. Set ENABLE bit (TX PSK MODE Register $E7) to ‘1’. The first byte of data will now be transmitted by the
device.
7. Wait for a TX DATA READY generated interrupt (read FLAGS to check and clear the IRQ).
8. Load next TX DATA BYTE.
9. Go to 7.
Note: The transmission should be terminated by setting the ENABLE bit (TX PSK MODE Register) to ‘0’.
5.4 Software Protocol for Receiving PSK Data Bytes
1. With the device out of ‘Zero Power’ mode, set up all receiver-related functions: Gain, HI/LO Band,
Equalization, UART mode, etc.
2. Perform a dummy read of the Rx DATA BYTE Register ($EA) and discard the result.
3. Read FLAGS Register ($EF) in order to clear it.
4. Set IRQ MASK BITS Register ($EE Bits 7, 4 and 3) to allow appropriate interrupts (RX PARITY,
RX DATA OVERFLOW and RX DATA READY).
5. Set ENABLE bit (RX PSK MODE Register $E8) to ‘1’.
6. Wait for an RX DATA READY generated interrupt (read FLAGS to check and clear the IRQ).
7. Read RX DATA BYTE ($EA).
8. Go to 5.
2000 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480197.006
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
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