CMX644AD5 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX644AD5' PDF : 34 Pages View PDF
V22 and Bell 212A Modem
CMX644A
IRQ MASK BITS ($EE)
This register is used to control the interrupts (IRQs) as described below:
RX PARITY mask
(Bit 7)
When this bit is set to ‘1’ it enables an interrupt that occurs when the RX
PARITY flag (Bit 7, FLAGS Register, $EF) changes from ‘0’ to ‘1’ i.e.
there is an RX PARITY error. When this bit is ‘0’ the interrupt is
masked.
RING DETECT mask
(Bit 6)
When this bit is set to ‘1’ it enables an interrupt that occurs when RING
DETECT CHANGE flag (Bit 6, FLAGS Register, $EF) changes from ‘0’
to ‘1’. When this bit is ‘0’ the interrupt is masked.
DETECT mask
(Bit 5)
When this bit is set to ‘1’ it enables an interrupt that occurs when
DETECT flag (Bit 5, FLAGS Register, $EF) changes from ‘0’ to ‘1’.
When this bit is ‘0’ the interrupt is masked.
RX DATA OVERFLOW
mask (Bit 4)
When this bit is set to ‘1’ it enables an interrupt that occurs when RX
DATA OVERFLOW flag (Bit 4, FLAGS Register, $EF) changes from ‘0’
to ‘1’. When this bit is ‘0’ the interrupt is masked.
RX DATA READY mask
(Bit 3)
When this bit is set to ‘1’ it enables an interrupt that occurs when RX
DATA READY flag (Bit 3, FLAGS Register, $EF) changes from ‘0’ to ‘1’.
When this bit is ‘0’ the interrupt is masked.
TX DATA UNDERFLOW
mask (Bit 2)
When this bit is set to ‘1’ it enables an interrupt that occurs when TX
DATA UNDERFLOW flag (Bit 2, FLAGS Register, $EF) changes from
‘0’ to ‘1’. When this bit is ‘0’ the interrupt is masked.
TX DATA READY mask
(Bit 1)
When this bit is set to ‘1’ it enables an interrupt that occurs when TX
DATA READY flag (Bit 1, FLAGS Register, $EF) changes from ‘0’ to ‘1’.
When this bit is ‘0’ the interrupt is masked.
UNSCRAM MARK mask
(Bit 0)
When this bit is set to ‘1’ it enables an interrupt that occurs when
UNSCRAM MARK flag (Bit 0, FLAGS Register, $EF) changes from ‘0’
to ‘1’. When this bit is ‘0’ the interrupt is masked.
© 2000 Consumer Microcircuits Limited
17
D/644A/6
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