CMX649 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX649' PDF : 50 Pages View PDF
ADM Codec
CMX649
C-BUS Timing (see Figure 14)
tCSE
CSN Enable to SClk high time
tCSH
Last SClk high to CSN high time
tLOZ
SClk low to ReplyData Output Enable
Time
tHIZ
tCSOFF
tNXT
tCK
tCH
tCL
tCDS
tCDH
tRDS
tRDH
CSN high to ReplyData high impedance
CSN high time between transactions
Inter-byte time
SClk cycle time
SClk high time
SClk low time
Command Data setup time
Command Data hold time
Reply Data setup time
Reply Data hold time
Notes Min. Typ. Max. Unit
100
ns
100
ns
0.0
ns
1.0
µs
1.0
µs
200
ns
200
ns
100
ns
100
ns
75
ns
25
ns
50
ns
0
ns
Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the
peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral
MSB (Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into the peripheral on the rising SERIAL_CLOCK edge.
3. Commands are acted upon at the end of each command (rising edge of CSN).
4. To allow for differing µC serial interface formats C-BUS compatible ICs are able to work
with SERIAL_CLOCK pulses starting and ending at either polarity.
5. Maximum 30pF load on IRQN pin and each C-BUS interface line.
These timings are for the CMX649, and allow faster transfers than the original C-BUS specification.
For codec data interface timing specifications and diagrams please refer to section 6.2.
© 2003 CML Microsystems Plc
48
D/649/2
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