CMX808AP4 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX808AP4' PDF : 23 Pages View PDF
Family Radio CTCSS 'Type 2' Encoder and Decoder
1.7.1 Electrical Performance (continued)
Timing Diagrams
CMX808A
Figure 6 "C-BUS" Timing
For the following conditions unless otherwise specified:
Xtal Frequency = 4.0MHz, VDD = 3.0V to 5.0V, Tamb = -40°C to +85°C.
Parameter
tCSE
tCSH
tHIZ
tCSOFF
tNXT
tCK
"CS-Enable to Clock-High"
Last "Clock-High to CS-High"
"CS-High to Reply Output 3-state"
"CS-High" Time between transactions
"Inter-Byte" Time
"Clock-Cycle" time
Notes
Min.
2.0
4.0
-
2.0
4.0
2.0
Typ.
Max.
-
-
2.0
-
-
-
Units
µs
µs
µs
µs
µs
µs
Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the
peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB
(Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing µController serial interface formats "C-BUS" compatible ICs are able to
work with either polarity SERIAL CLOCK pulses.
2003 CML Microsystems Plc
20
D/808A/6
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