CMX838D1 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX838D1' PDF : 71 Pages View PDF
FRS/PMR446/GMRS Family Radio Processor
CMX838
Operating Characteristics Notes:
1. At VDD = 3.0V and TAMB = 25°C only. Currents change with VDD.
2. Not including any current drawn from the device by external circuitry.
3. IRQ pin.
4. With input gain components set as recommended in Figure 2 and internal gains set to 0dB.
5. Measured at MOD 1 or MOD 2 output.
6. See Section 4.1.
7. Maximum internal signal gains are about 11dB for the pre-emphasis filter and 12dB for de-emphasis,
thus to avoid supply rails and clipping, signals should be scaled appropriately. The +/-7.5dB audio
level amplifier can be used to scale signals for best sound quality. Filter supply rails are approximately
VDD-0.3V. For example to minimize the de-emphasis filter distortion at VDD = 3.0V keep signals below
about
VDD
− 0.3
dB _ gain
=240mVRMS at its
input
2 ⋅ 2 ⋅10 20
8. Resistive load of 10kΩ, at VDD = 3.0V and TAMB = 25°C.
9. Timing for an external input to the XTAL/CLOCK pin.
10. Variation over voltage, temperature, and frequency.
11. Level is independent of supply voltage.
7.1.4 Timing
C-BUS Timings (See Figure 48)
tCSE
CS -Enable to Clock-High time
tCSH
Last Clock-High to CS -High time
tLOZ
Clock-Low to Reply Output enable time
tHIZ
CS -High to Reply Output 3-state time
tCSOFF
CS -High Time between transactions
tNXT
Inter-Byte Time
tCK
Clock-Cycle time
tCH
Serial Clock-High time
tCL
Serial Clock-Low time
tCDS
Command Data Set-Up time
tCDH
Command Data Hold time
tRDS
Reply Data Set-Up time
tRDH
Reply Data Hold time
Maximum 30pF load on each C-BUS interface line.
Notes
Min.
100
100
0.0
-
1.0
200
200
100
100
75.0
25.0
50.0
0.0
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
-
-
-
1.0
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Note: These timings are for the latest version of the C-BUS as embodied in the CMX838.
2003 CML Microsystems Plc
68
D/838/8
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