CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
TIME0, 1, 2, 3 (all 32 bits):
These bits are not affected by either power-up reset or RESETN; they are indeterminate on power-up.
ALM0, 1, 2, 3 (all 32 bits):
These bits are not affected by either power-up reset or RESETN; they are indeterminate on power-up.
SBUF b7..0:
A standard 8051 µC register (UART data buffer). The bits of this register are not affected by either power-
up reset or RESETN: they are indeterminate on power-up.
1.4.4 Local BOOT ROM
The CMX850 can be configured to execute the “thin stub” code, which resides in the on-chip BOOT ROM,
instead of the normal program contained in the user’s external ROM. This “thin stub” code will download a
“thick stub” code from the serial port, place it in XRAM and execute it. The template for the “thick stub”
code is supplied by CML to enable customers to create a “thick stub” for the purposes of reprogramming
FLASH memory, which the user may fit in place of external ROM. An 11.0592 MHz xtal must be used to
obtain the standard 19,200 baud rate, in order to reprogram FLASH memory from the 8051 µC serial port.
This baud rate is fixed by the "thin stub" code and the chip reset mechanism. It is not variable. Please
contact CML Technical Support for details of suitable FLASH memories.
To execute the BOOT ROM program:
1. Make sure the device is powered up.
2. Apply reset by pulling the RESETN pin low for a minimum of two seconds.
3. While reset is active, short the VBIAS pin to the analogue VDD supply. This can be done with a
wire link or an active device (the voltage on the VBIAS pin must be no lower than
VDD – 0.1V). Note that while reset is active, the VBIAS pin looks like a 50kΩ (nominal) resistor to
VSS in parallel with the off-chip decoupling capacitor.
4. Remove reset from the device by taking the RESETN pin high. The voltage on the VBIAS pin
must be held for at least 1µs. The device will then boot up from the internal BOOT ROM.
5. To get the device out of “BOOT ROM” mode it must be reset again with the connection between
VBIAS and VDD removed (so that the voltage on the VBIAS pin is less than ½VDD). Alternatively,
a reset pulse of less than 0.4 seconds will get the device out of “BOOT ROM” mode, whatever
voltage is on the VBIAS pin.
1.4.5 Line Interface
A line interface circuit is needed to provide dc isolation and to terminate the line.
2-Wire Line Interface
Figure 4a shows an interface for use with a USA 600Ω 2-wire line. The complex line termination is provided
by R10, R13, C17, C18, C19 and C24, high frequency noise is attenuated by C23 and C24, while R11 and
R12 set the receive signal level into the modem. R14 connects in parallel with R11 when enabled in the
Analogue Signal Path Register. This is for the purpose of increasing gain, which is necessary to
compensate for signal attenuation during on-hook CLI detection. Tx rejection into the Rx is provided by
R15. For clarity, not all of the 2-wire line protection circuits have been shown. Components for use in other
countries vary by country.
© 2003 CML Microsystems Plc
14
D/850/6
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