CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5.3 I/O Ports
The 8051 µC port structure within the CMX850 has been enhanced by the addition of two extra byte-wide
ports, port 4 and port 5. The ports have also been enhanced for low power operation by the addition of
explicit port direction control registers, which means that port input pins consume no dc current when driven
with a logic 0 (standard 8051 port inputs consume several tens of microamps of dc current per pin when
driven with a logic 0). To further enhance flexibility, all of the port 1, 3, 4 and 5 pins can be individually
configured as open-drain output drivers, and with optional pull-up resistors.
The port configuration within the CMX850 is shown in Table 2. Note that, in order for port bit P3.1 (TXD) to
be used to output serial port data or clock pulses in mode 0-3, both the P3 output latch bit 1 and the P3DIR
direction latch bit 1 must be loaded with a logic 1. Similarly, in order for port bit P3.0 (RXD) to be used to
output serial port data in mode 0, both the P3 output latch bit 0 and the P3DIR direction latch bit 0 must be
loaded with a logic 1.
Port
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Function
When the CMX850 is configured with a multiplexed external memory interface (pin
MUXAD = 1), port 0 bits 2-0 are available as I/O pins. The remaining port 0 bits (7-
3) are unused. Note that the port 0 pins do not have memory address/data driven
onto them during an external memory access, as would happen on a standard 8051:
the CMX850 external memory interface is completely separate from the port 0
circuit.
Port 1 bits 7-0 are available as I/O pins. They are automatically configured as
keyboard row input pins with pull-up resistors when the keyboard encoder is
enabled.
Port 2 bits 7-0 are not available directly as I/O pins, but the contents of the byte-
wide port 2 output latch is used during MOVX A,@Ri and MOVX @Ri,A instructions
to form the upper eight address bits on pins A15-8. This is done to maintain
compatibility with the standard 8051 µC instruction set.
Port 3 bits 7-0 are available as I/O pins. Each pin also has an alternative output
function, as shown below. Pins P3.6 and P3.7 are automatically configured as an
output when the associated PWM block is enabled. The other alternative pin
functions require the correct pin direction to be explicitly configured using the
P3DIR register.
Port
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternative function
RXD (Serial port receive data)
TXD (Serial port transmit data)
Int0 (External interrupt 0)
Int1 (External interrupt 1)
T0 (Timer/counter 0 external input)
T1 (Timer/counter 1 external input)
PWM1 (Pulse-width modulator 1 output)
PWM2 (Pulse-width modulator 2 output)
Port 4 bits 7-0 are available as I/O pins. Between one and eight port 4 pins are
automatically configured as open-drain column drivers when the keyboard encoder
is enabled, depending on the contents of the KBCON register.
Port 5 bits 7-0 are available as I/O pins (bits 7-5 are only available if the CMX850 is
configured with a multiplexed external memory interface). Up to eight port 5 pins are
automatically configured as open-drain column drivers when the keyboard encoder
is enabled, depending on the contents of the KBCON register.
Table 2 I/O Port Function
© 2003 CML Microsystems Plc
20
D/850/6
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