CMX867E2 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX867E2' PDF : 45 Pages View PDF
Low Power V.22 Modem
CMX867
General Control Register b8: Powerup
This bit controls the internal power supply to most of the internal circuits, including the Xtal
oscillator and VBIAS supply. Note that the General Reset command clears this bit, putting the
device into Powersave mode.
b8 = 1
b8 = 0
Device powered up normally
Powersave mode (all circuits except Ring Detect, RDRVN and C-BUS
interface disabled)
When the power is first applied to the device, the following powerup procedure should be
followed to ensure correct operation.
i.
(Power is applied to the device)
ii.
Issue a General Reset command
iii.
Write to the General Control Register (address $E0) setting both the Powerup bit
(b8) and the Reset bit (b7) to 1 – leave in this state for a minimum of about 20ms –
it is required that the crystal initially runs for this time in order to clock the internal
logic into a defined state. The device is now powered up, with the crystal and VBIAS
supply operating, but is otherwise not running any transmit or receive functions.
iv. The device is now ready to be programmed as and when required. Examples:
• A General Reset command could be issued to clear all the registers and
therefore powersave the device.
• The Reset bit in the General Control Register could be set to 0 as part of a
routine to program all the relevant registers for setting up a particular operating
mode.
When the device is switched from Powersave mode to normal operation by setting the
Powerup bit to 1, the Reset bit should also be set to 1 and should be held at 1 for about 20ms
while the internal circuits, Xtal oscillator and VBIAS stabilise before starting to use the transmitter
or receiver.
General Control Register b7: Reset
Setting this bit to 1 resets the CMX867’s internal circuitry, clearing all bits of the Transmit and
Receive Mode Registers and b13-0 of the Status Register.
b7 = 1
b7 = 0
Internal circuitry in a reset condition.
Normal operation
General Control Register b6: IRQNEN (IRQN O/P Enable)
Setting this bit to 1 enables the IRQN output pin.
b6 = 1
b6 = 0
IRQN pin driven low (to VSS) if the IRQ bit of the Status Register = 1
IRQN pin disabled (high impedance)
General Control Register b5-0: IRQ Mask bits
These bits affect the operation of the IRQ bit of the Status Register as described in section
1.5.10.7
© 2004 Consumer Microcircuits Limited
21
D/867/5
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