CMX868E2 View Datasheet(PDF) - MX-COM Inc
Part Name
Description
MFG CO.
'CMX868E2' PDF : 43 Pages View PDF
Low Power V.22bis Modem
14
CMX868 Advance Information
The FSK demodulator recognizes individual frequencies as representing received ‘1’ or ‘0’ data bits:
The QAM/DPSK demodulator decodes QAM or DPSK modulation of a 1200Hz or 2400Hz carrier and is used
for V.22, V.22bis and Bell 212A modes. It includes an adaptive receive signal equalizer (auto-equalizer) that
will automatically compensate for a wide range of line conditions in both QAM and DPSK modes. The auto-
equalizer can provide a useful improvement in performance in 600 or 1200bps DPSK modes as well as
2400bps QAM, so although it must be disabled at the start of a handshake sequence, it can be enabled as
soon as scrambled 1200bps 1s have been detected.
Both FSK and QAM/DPSK demodulators produce a serial data bit stream that is fed to the Rx pattern
detector, descrambler and USART block. See Figure 14. In QAM/DPSK modes the demodulator input is also
monitored for the v.22bis handshake signal ‘S1” signal.
The QAM/DPSK demodulator also estimates the received bit error rate by comparing the actual received
signal against an ideal waveform. This estimate is placed in bits 2-0 of the Status Register. See Figure 19.
4.8 Rx Modem Pattern Detectors and Descrambler
Reference Figure 14.
The 1010.. pattern detector operates only in FSK modes and will set bit 9 of the Status Register when 32 bits
of alternating 1’s and 0’s have been received.
The ‘Continuous Unscrambled 1’s’ detector operates in all modem modes and sets bits 8 and 7 of the Status
Register to ‘01’ when 32 consecutive 1’s have been received.
The descrambler operates only in DPSK/QAM modes and is enabled by setting bit 7 of the Rx Mode Register.
The ‘Continuous Scrambled 1’s’ detector operates only in DPSK/QAM modes when the descrambler is
enabled and sets bits 8 and 7 of the Status Register to ‘11’ when 32 consecutive 1’s appear at the output of
the descrambler. To avoid possible ambiguity, the ‘Scrambled 1’s’ detector is disabled when continuous
unscrambled 1’s are detected.
The ‘Continuous 0’s’ detector sets bits 8 and 7 of the Status Register to ‘10’ when NX consecutive 0’s have
been received, NX being 32 except when DPSK/QAM Start-Stop mode has been selected, in which case
NX = 2N + 4 where N is the number of bits per character including the Start, Stop and any Parity bits.
All of these pattern detectors will hold the ‘detect’ output for 12 bit times after the end of the detected pattern
unless the received bit rate or operating mode is changed, in which case the detectors are reset within 2ms.
¤2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480205.007
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
Share Link: 
