CMX868E2 View Datasheet(PDF) - MX-COM Inc
Part Name
Description
MFG CO.
'CMX868E2' PDF : 43 Pages View PDF
Low Power V.22bis Modem
26
CMX868 Advance Information
4.10.7 Status Register: 16-bit read-only C-BUS address $E6
Bits 15 and 13-0 of this register are cleared to 0 by a General Reset command, in Powersave mode, or when
b7 (Reset) of the General Control Register is 1.
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IRQ RD PF
See below for uses of these bits
The meanings of the Status Register bits 12-0 depend on whether the receive circuitry is in Modem or Tones
Detect mode.
Status Register bits:
Rx Modem modes
Rx Tones Detect modes
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
IRQ
Set to 1 on Ring Detect
Programming Flag bit. See Section 4.10.8
Set to 1 on Tx data ready.
Cleared by write to Tx Data Register
Set to 1 on Tx data underflow.
Cleared by write to Tx Data Register
1 when energy is detected in Rx
modem signal band
1 when energy is detected in Call
Progress band or when both
programmable tones are detected
1 when S1 pattern (double DPSK 0
dibit 00,11) is detected in DPSK or
QAM modes, or when ‘1010..’
pattern is detected in FSK modes
See following table
0
See following table
1 when 2100Hz answer tone or the
second programmable tone is
detected
Set to 1 on Rx data ready.
Cleared by read from Rx Data
Register
1 when 2225Hz answer tone or the
first programmable tone is detected
Set to 1 on Rx data overflow.
Cleared by read from Rx Data
Register
1 when DTMFcode is detected
Set to 1 on Rx framing error
0
Set to 1 on even Rx parity
Rx DTMF code b3, see table
QAM/DPSK Rx signal quality b2
Rx DTMF code b2
QAM/DPSK Rx signal quality b1
Rx DTMF code b1
QAM/DPSK Rx signal quality b0
or FSK frequency demodulator
output
Rx DTMF code b0
** IRQ
Mask bit
Bit 5
Bit 4
Bit 3
Bit 3
Bit 2
b1
b1
b1
b0
b0
-
-
-
-
-
Note: ** This column shows the corresponding IRQ Mask bits in the General Control Register. A 0 to 1
transition on any of the Status Register bits 14-5 will cause the IRQ bit b15 to be set to 1 if the corresponding
IRQ Mask bit is 1. The IRQ bit is cleared by a read of the Status Register or a General Reset command or by
setting b7 or b8 of the General Control Register to 1.
A spurious ‘continuous 0s’ detect may be generated within 4ms of changing the Rx Mode Register to any of
the QAM or DPSK modes.
The operation of the data demodulator and pattern detector circuits within the CMX868 does not depend on
the state of the Rx energy detect function.
¤2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 20480205.007
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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