CMX882 View Datasheet(PDF) - CML Microcircuits
Part Name
Description
MFG CO.
'CMX882' PDF : 70 Pages View PDF
FRS Signalling Processor
CMX882
1.6.15
Bit:
$CE INTERRUPT MASK: 16-bit write-only
15
14
13
12
11
10
9
8
IRQ
MASK
0
Rx In-band
detect MASK
XTCSS MASK
Rx CTCSS
detect MASK
Rx DCS Aux ADC High Aux ADC Low
detect MASK
MASK
MASK
Bit:
7
6
5
4
3
2
FFSK end Data transfer
MASK
MASK
0
Rx 2400b/s Rx 1200b/s
detect MASK detect MASK
0
1
0
0
Prog Flag
MASK
Bit
Value Function
15
1 Enable selected interrupts
0 Disable all interrupts (IRQN pin not activated)
14
Reserved – Set to 0
13
1 Enable interrupt when a change to a In-band tone is detected as indicated
by a '0' to '1' change of bit 13 of the Status register
0 Disabled
12
1 Enable interrupt when a valid XTCSS 4 tone set is detected or has
finished being transmitted as indicated by a '0' to '1' change on bit 12 of
the Status register
0 Disabled
11
1 Enable interrupt when a change to a programmed CTCSS tone is
detected as indicated by a '0' to '1' change of bit 11 of the Status register
0 Disabled
10
1 Enable interrupt on a change in the detect status of the DCS decoder as
indicated by a '0' to '1' change of bit 10 of the Status register
0 Disabled
9, 8
1 Enable interrupt when the corresponding Aux ADC status bit changes
0 Disabled
7
1 Enable interrupt when FFSK data transmission has ended
0 Disabled
6
1 Enable interrupt when an FFSK data transfer is required
0 Disabled
5
Reserved - Set to 0
4
1 Enable interrupt when valid 2400b/s data is detected
0 Disabled
3
1 Enable interrupt when valid 1200b/s data is detected
0 Disabled
2, 1
Reserved - Set to 0
0
1 Enable interrupt when Prog Flag bit of the Status register changes from '0'
to '1' (see Programming register $C8)
0 Disabled
2004 CML Microsystems Plc
46
D/882/7
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