COM20019I3V-DZD View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'COM20019I3V-DZD' PDF : 70 Pages View PDF
RAM
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
D0-D7
Data Register
I/O Address 04H
Memory
Data Bus
8
Address Pointer Register
I/O Address 02H I/O Address 03H
High
Low
11-Bit Counter
Memory
Address Bus
11
2K x 8
INTERNAL
RAM
Figure 6.1 - SEQUENTIAL ACCESS OPERATION
6.3
INTERNAL RAM
The integration of the 2K x 8 RAM in the COM20019I 3V represents significant real estate savings. The
most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the
integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external
latch, and multiplexed address/data bus and control functions which were necessary to interface to the
RAM. The integration of RAM represents significant cost savings because it isolates the system designer
from the changing costs of external RAM and it minimizes reliability problems, assembly time and costs,
and layout complexity.
6.3.1 Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory,
the internal RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is
Rev. 10-31-06
Page 36
DATASHEET
SMSC COM20019I 3.3V Rev.C
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