COM20019I3V-DZD View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'COM20019I3V-DZD' PDF : 70 Pages View PDF
RAM
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
A0-A2
nCS
nRD
nWR
D0-D7
VALID
t1
t2
t3
Note 3
t10
t6
t5
t8
VALID DATA
t4
t9
Note 2
t7
CASE 1: RBUSTMG bit = 0
Parameter
t1 Address Setup to nRD Active
t2 Address Hold from nRD Inactive
t3 nCS Setup to nRD Active
t4 nCS Hold from nRD Inactive
t5 Cycle Time (nRD Low to Next Time Low)
t6 nRD Low to Valid Data
t7 nRD High to Data High Impedance
t8 nRD Low Width
t9 nRD High Width
t10 nWR to nRD Low
min
15
10
5**
0
4TARB*
0
60
20
20
max
40**
20
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
* TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
** nCS may become active after control becomes active, but the access time (t6)
will now be 45nS measured from the leading edge of nCS.
Note 1: The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
**Note 2: Read cycle for Address Pointer Low/High Registers occurring after a read from
Data Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of the next nRD.
Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to
Data Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of nRD.
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE
Rev. 10-31-06
Page 54
DATASHEET
SMSC COM20019I 3.3V Rev.C
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