CRD8900-1 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CRD8900-1' PDF : 132 Pages View PDF
CS8900
Register 12: Transmit Collision Counter (TxCOL, Read-only)
Address: PacketPage base + 0132h
F-6
ColCount
5-0
010010
The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) or
AUI Collision Pair (CI+ / CI-) becomes active while a packet is being transmitted. If the TxColOvfiE bit (Register
B, BufCFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides
the host with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by
interrupting at 200h, the host has an additional 512 counts before TxCOL actually overflows). The TxCOL counter
is cleared when read.
BIT NAME
DESCRIPTION
5-0 010010
These bits provide an internal address used by the CS8900 to identify this as the Bus
Status Register. When reading this register, these bits will be 010010, where the LSB
corresponds to Bit 0.
F-6 ColCount
The upper ten bits contain the number of collisions.
This register’s initial state after reset is: 0000 0000 0001 0010
DS150PP2
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