CRD8900-1 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CRD8900-1' PDF : 132 Pages View PDF
CS8900
4.7 Receive and Transmit Frame
Locations
The Receive and Transmit Frame PacketPage lo-
cations are used to transfer Ethernet frames to
and from the host. The host sequentially writes
to and reads from these locations, and internal
buffer memory is dynamically allocated between
transmit and receive as needed. One receive
frame and one transmit frame are accessible at a
time.
Receive PacketPage Locations
In IO mode, the receive status/length/frame loca-
tions are read through repetitive reads from one
IO port at the IO base address. See Section 4.10.
In memory mode, the receive status/length/frame
locations are read using memory reads of a block
of memory starting at memory base address +
0400h. Typically the memory locations are read
sequentially using repetitive Move instructions
(REP MOVS). See Section 4.9.
Random access is not needed. However, the first
118 bytes of the receive frame can be accessed
randomly if word reads, on even word bounda-
ries, are used. Beyond 118 bytes, the memory
reads must be sequential. Byte reads, or reads on
odd-word boundaries, can be performed only in
sequential read mode. See Section 4.8.
The RxStatus word reports the status of the cur-
rent received frame. RxEvent register 4
(PacketPage base + 0124h) has the same contents
as the RxStatus register, except RxEvent is
cleared when RxEvent is read.
The RxLength (receive length) word is the
length, in bytes, of the data to be transferred to
the host across the ISA bus. The register de-
scribes the length from the start of Source
Address to the end of CRC, assuming that CRC
has been selected (via Register 3 RxCFG, bit
BufferCRC). If CRC has not been selected, then
the length does not include the CRC, and the
CRC is not present in the receive buffer.
After the RxLength has been read, the receive
frame can be read. When some portion of the
frame is read, the entire frame should be read
before reading the RxEvent register either di-
rectly or through the ISQ register. Reading the
RxEvent register signals to the CS8900 that the
host is finished with the current frame, and wants
to start processing the next frame. In this case,
the current frame will no longer be accessible to
the host. The current frame will also become in-
accessible if a Skip command is issued, or if the
entire frame has been read. See Section 5.2.
Transmit Locations
The host can write frames into the CS8900 buff-
er using Memory writes using REP MOVS to the
TxFrame location. See Section 5.7.
4.8 Eight and Sixteen Bit Transfers
A data transfer to or from the CS8900 can be
done in either I/O or Memory space, and can be
either 16 bits wide (word transfers) or 8 bits
wide (byte transfers). Because the CS8900’s in-
ternal architecture is based on a 16-bit data bus,
word transfers are the most efficient.
The CS8900 does not support connection to 8-bit
buses.
To transfer transmit frames to the CS8900 and
receive frames from the CS8900, the host may
mix word and byte transfers, provided it follows
three rules:
1. The primary method used to access CS8900
memory is word access.
2. Word accesses to the CS8900’s internal mem-
ory are kept on even-byte boundaries.
DS150PP2
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