CS2100-CP-CZZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS2100-CP-CZZ' PDF : 32 Pages View PDF
CS2100-CP
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF.
Parameter
Symbol
Min
Max
CCLK Clock Frequency
fccllk
-
6
CCLK Edge to CS Falling
(Note 12)
tspi
500
-
CS High Time Between Transmissions
tcsh
1.0
-
CS Falling to CCLK Edge
tcss
20
-
CCLK Low Time
tscl
66
-
CCLK High Time
tsch
66
-
CDIN to CCLK Rising Setup Time
tdsu
40
-
CCLK Rising to DATA Hold Time
(Note 13)
tdh
15
-
Rise Time of CCLK and CDIN
(Note 14)
tr2
-
100
Fall Time of CCLK and CDIN
(Note 14)
tf2
-
100
Delay from Supply Voltage Stable to Control Port Ready
tdpor
100
-
Unit
MHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
µs
Notes: 12. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For fcclk < 1 MHz.
VD
tdpor
CS
CCLK
CDIN
t spi tcss
t scl t sch
tcsh
t r2
t f2
t dsu tdh
Figure 3. Control Port Timing - SPI Format (Write Only)
DS840PP1
9
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