CS42L52-CNZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS42L52-CNZR' PDF : 82 Pages View PDF
5/13/08
CS42L52
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.
Parameters
RESET pin Low Pulse Width
MCLK Frequency (Note 15)
Symbol
(Note 14)
MCLK Duty Cycle
Slave Mode
Input Sample Rate (LRCK)
Fs
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
Output Sample Rate (LRCK)
1/tP
ts(LK-SK)
td(MSB)
ts(SDO-SK)
th(SK-SDO)
ts(SD-SK)
th
All Speed Modes Fs
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
SCLK=MCLK mode 1/tP
MCLK=12.0000 MHz 1/tP
all other modes 1/tP
td(MSB)
ts(SDO-SK)
th(SK-SDO)
ts(SD-SK)
th
Min
Max
1
-
(See “Serial Port Clock-
ing” on page 34)
45
55
(See “Serial Port Clock-
ing” on page 34)
45
55
-
64•Fs
45
55
40
-
-
52
20
-
30
-
20
-
20
-
(See “Serial Port Clock-
ing” on page 34)
45
55
-
12.0000
-
68•Fs
-
64•Fs
45
55
-
52
20
-
30
-
20
-
20
-
Units
ms
MHz
%
kHz
%
Hz
%
ns
ns
ns
ns
ns
ns
Hz
%
MHz
Hz
Hz
%
ns
ns
ns
ns
ns
14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are
settled.
15. See “Example System Clock Frequencies” on page 76 for typical MCLK frequencies.
LRCK
SCLK
SDOUT
SDIN
ts(LK-SK)
td(MSB)
ts(SD-SK)
//
//
tP
//
//
th(SK-SDO)
//
MSB
//
th
//
MSB
//
ts(SDO-SK)
MSB-1
MSB-1
Figure 3. Serial Audio Interface Timing
DS680F1
21
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